MC9S12XEP100 oscillator problem (sw/hw)

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MC9S12XEP100 oscillator problem (sw/hw)

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Contributor I

Hi all.

 

I have a problem when I try to program MCU with 4MHz oscillator. It works when the oscillator is not used.

 

Setup:

CodeWarrior 5.9.0

Vdd: 3.3 V

MCU: MC9S12XEP100-144

External oscillator: http://datasheet.octopart.com/ASV-48.000MHZ-EJ-T-Abracon-datasheet-5458457.pdf  (4MHz)

External oscillator output: amplitude is ~ 3.2 V (square wave).

Output of the oscillator has a voltage divider with resistors and capacitor. Oscillator gives ~1.95 V amplitude to EXTAL pin.

XTAL is not connected. VDDpll is bypassed to ground.

 

Code I'm using to program PLL:

void SetupPLL(void)

{

  // SYNR_SETUP = 0x04 (SYNDIV[1])

  SYNR = SYNR_SETUP;

// REFDV_SETUP = 0x04 (REFFRQ[1])

  REFDV = REFDV_SETUP;

// POSTDIV_SETUP = 0

  POSTDIV = POSTDIV_SETUP;

  

  // wait for the PLL to lock into correct frequency

  while(!(CRGFLG & CRGFLG_LOCK_MASK));

 

  // CLKSEL_SETUP = 0x80 (PLLSEL[1])

  CLKSEL = CLKSEL_SETUP;

 

 

  // Check if everything is ok

  while(!(CLKSEL & CLKSEL_PLLSEL_MASK));

}

 

When oscillator is connected and SetupPLL function is used, the programmer gives verification error @ 0x0000C008.

Also, I have came across with illegal breakpoints and xgate breakpoints. At first I couldn't find the right delay for programming even if automatic delay was used, but when I increased the output voltage from oscillator it started to work. I can use steps until init() functions when it crashes.

 

When both oscillator and SetupPLL are not used, I can program the MCU without any problems.

 

I have tried to use signal generator (Vpp 1.8v: 0-1.8 V, 4MHz, same code,) for EXTAL pin, but it didn't work.

 

If you have any experience about these kind of problems or you could share some ideas how to proceed with this system, I'd be grateful.

 

-Taavi

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NXP TechSupport
NXP TechSupport

VDDPLL max = 1.98V 

EXTAL max = VDDPLL + 0.3V ; you have 1.95V => OK

VDDPLL must be connected to GND via C=220nF ; You have written VDDpll is bypassed to ground. => ???

I suppose  you have \XCLKS connected to GND (log.0)

In order to calculate PLL setup the easiest way is to use: https://community.freescale.com/docs/DOC-103954

short example for PLL setup:

//==============================================================================

// The example present PLL setup example

// OSCCLK=16MHz

//==============================================================================

#include <MC9S12XEP100.h>     /* derivative information */

#pragma LINK_INFO DERIVATIVE "mc9s12xep100"

//==============================================================================

void set_pll(unsigned char _synr, unsigned char _refdv, unsigned char _postdiv);

//==============================================================================

void set_pll(unsigned char _synr, unsigned char _refdv, unsigned char _postdiv)

{

  PLLCTL = 0B00000001; // CME=0,PLLON=0,FM1=0,FM2=0,FSTWKP=0,PRE=0,PCE=0,SCME=1

  CLKSEL = 0B00000011; // PLLSEL=0,PSTP=0,PLLWAI=0,RTIWAI=1,COPWAI=1

  SYNR = _synr;        // Set the multiplier register

  REFDV = _refdv;      // Set the divider register

  POSTDIV = _postdiv;  // Set the post divider register

  PLLCTL_PLLON = 1;    // Enable the Phase Lock Loop

  while(!CRGFLG_LOCK); // Wait till the PLL VCO is within tolerance

  CLKSEL_PLLSEL = 1;   // Select clock source from PLLCLK

 

ECLKCTL_NECLK=0;     // Enable the BusClk output at ECLK pin to see busclk if necessary

}

//==============================================================================

void set_plloff(unsigned char _synr, unsigned char _refdv, unsigned char _postdiv)

{

  PLLCTL = 0B00000001; // CME=0,PLLON=0,FM1=0,FM2=0,FSTWKP=0,PRE=0,PCE=0,SCME=1

  CLKSEL = 0B00000011; // PLLSEL=0,PSTP=0,PLLWAI=0,RTIWAI=1,COPWAI=1

  SYNR = _synr;        // Set the multiplier register

  REFDV = _refdv;      // Set the divider register

  POSTDIV = _postdiv;  // Set the post divider register

  PLLCTL_PLLON = 1;    // Enable the Phase Lock Loop

  while(!CRGFLG_LOCK); // Wait till the PLL VCO is within tolerance

  CLKSEL_PLLSEL = 0;   // Select clock source from PLLCLK

 

ECLKCTL_NECLK=0;     // Enable the BusClk output at ECLK pin to see busclk if necessary

}

//==============================================================================

void main(void)

{

//set_pll(0xD8, 0x01, 0x00); // BUSCLK=50MHz from OSCCLK=4MHz

//set_pll(0x05, 0x40, 0x00); // BUSCLK=24MHz from OSCCLK=4MHz

set_pll(0x05, 0x40, 0x00); // BUSCLK=24MHz from OSCCLK=4MHz

  DDRB = 0xFF;

  for(;;)

    {

      PORTB = ~PORTB;

    }

}

To check the schematic look into attachment.

Best regards,

Ladislav

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