I gave things a bit of a rest to see if that might help with troubleshooting. As an experiment I disconnected all of my external pots so all that was connected to the ATD pins was the battery voltage sensing circuit on Ch0 and the output from the on board barometric pressure sensor on Ch7. When I did this the calculated battery voltage was still higher than it should be, as it was before, but the barometric pressure seemed to be correct. I don't know if it was before because I didn't do a calculation check then. Anyway, what I did notice was that all of the pins that had nothing connected to them all read either 1022 or 1023 counts. That doesn't seem right to me. It is almost as if there is a pull up somehow on all of the pins with the possible exception of Ch7. I went through all the things I could think of for the initialization process and modified my code. That didn't change anything. With the pots re-connected they all still read either 32 or 33 counts with no measurable voltage on the wires leading to the pins. The conversion sequence seems to operate normally. I've copied my initialization and application code below: Any opinions would be greatly appreciated.
Regards,
Robert
#macro INIT_ADC0, 0
;*****************************************************************************************
; - Initialize Analog to Digital Converter (ATD0) for continuous conversions
; 8.3MHz ATDCLK period = 0.00000012048 Sec.
; 10 bit ATD Conversion period = 41 ATDCLK cycles(ref page 1219)
; Sample time per channel = 24+2 for discharge capacitor = 26 ATDCLK cycles
; Sample time for 13 channels = (41+26)x13=871 ATDCLK periods = 0.000114810 Sec. (~115uS)
;*****************************************************************************************
movw #$1FFF,PT0AD0 ; Load Port AD0 Data Registers PT0AD0:PT1AD0
; with %0001111111111111 (General Purpose I/Os on pins 15,14,13
; ATD on pins 12,11,10,9,8,7,6,5,4,3,2,1,0)
;(Registers are %00000000 out of reset)
movw #$0000,DDR0AD0 ; Load Port AD0 Data Direction Registers DDR0AD0:DDR1AD0
; with %0000000000000000 (All pins inputs)
;(Registers are %00000000 out of reset)
movw #$0000,RDR0AD0 ; Load Port AD0 Reduced Drive Registers RDR0AD0:RDR1AD0
; with %0000000000000000 (Full Drive Strength Enabled)
;(Registers are 500000000 out of reset)
movw #$E000,PER0AD0 ; Load Port AD0 Pullup Enable Registers PER0AD0:PER1AD0
; with %1110000000000000 (Pullups enabled on pins 15,14,13
; Pullups disabled on pins 12,11,10,9,8,7,6,5,4,3,2,1,0)
;(Registers are %00000000 out of reset)
movb #$0C,ATD0CTL0 ; Load ATD0 Control Register 0 with %00001100
; (wrap after converting AN12)
; ^ ^
; WRAP-----+--+
;(Register is %00001111 out of reset)
movb #$30,ATD0CTL1 ; Load ATD Control Register 1 with %00110000
; (no external trigger, 10 bit resolution,
; discharge cap before conversion)
; ^^^^^ ^
;ETRIGSEL-+|||| |
; SRES--++|| |
; SMP_DIS----+| |
; ETRIGCH-----+--+
;(Register is %00001111 out of reset)
;* movb #$62,ATD0CTL2 ; Load ATD Control Register 2 with %01100010
;(fast flag clear, continue in stop,
; no external trigger, Sequence
; complete interrupt enabled,
; Compare interrupt disabled)
; ^^^^^^^
; AFFC--+||||||
; ICLKSTP---+|||||
; ETRIGLE----+||||
; ETRIGP-----+|||
; ETRIGE------+||
; ASCIE-------+|
; ACMPIE--------+
;(Register is %00000000 out of reset)
;* movb #$60,ATD0CTL2 ; Load ATD Control Register 2 with %01100000
;(fast flag clear, continue in stop,
; no external trigger, Sequence
; complete interrupt disabled,
; Compare interrupt disabled)
; ^^^^^^^
; AFFC--+||||||
; ICLKSTP---+|||||
; ETRIGLE----+||||
; ETRIGP-----+|||
; ETRIGE------+||
; ASCIE-------+|
; ACMPIE--------+
;(Register is %00000000 out of reset)
movb #$20,ATD0CTL2 ; Load ATD Control Register 2 with %00100000
;(no fast flag clear, continue in stop,
; no external trigger, Sequence
; complete interrupt disabled,
; Compare interrupt disabled)
; ^^^^^^^
; AFFC--+||||||
; ICLKSTP---+|||||
; ETRIGLE----+||||
; ETRIGP-----+|||
; ETRIGE------+||
; ASCIE-------+|
; ACMPIE--------+;
;(Register is %00000000 out of reset)
;* movb #$80,ATD0CTL3 ; Load ATD Control Register 3 with %10000000
;(right justifed data, 16 conversions,
; no Fifo, no freeze)
; ^^^^^^^^
; DJM-+|||||||
; S8C--+||||||
; S4C---+|||||
; S2C----+||||
; S1C-----+|||
; FIFO------+||
; FRZ-------++
;(Register is %00100000 out of reset)
movb #$82,ATD0CTL3 ; Load ATD Control Register 3 with %10000010
;(right justifed data, 16 conversions,
; no Fifo, Finish conversion before stop in freeze)
; ^^^^^^^^
; DJM-+|||||||
; S8C--+||||||
; S4C---+|||||
; S2C----+||||
; S1C-----+|||
; FIFO------+||
; FRZ-------++
;(Register is %00100000 out of reset)
movb #$E2,ATD0CTL4 ; Load ATD Control Register 4 with %11100010
;(24 cycle sample time, prescale = 2
; for 8.3MHz ATDCLK)
; ^ ^^ ^
; SMP-+-+| |
; PRS----+---+
;(Register is %00000101 out of reset)
movw #$1FFF,ATD0DIENH ; Load ATD0 Input Enable Register Hi byte and Lo byte with
; %000111111111111 (Disable input buffer pins 15,14,13
; Enable input buffer pins 12,11,10,9,8,7,6,5,4,3,2,1,0)
;(Register is %0000000000000000 out of reset)
;* movw #$E000,ATD0DIENH ; Load ATD0 Input Enable Register Hi byte and Lo byte with
; %1110000000000000 (Enable input buffer pins 15,14,13
; Disable input buffer pins 12,11,10,9,8,7,6,5,4,3,2,1,0)
;(Register is %0000000000000000 out of reset)
;* movw #$0000,ATD0DIENH ; Load ATD0 Input Enable Register Hi byte and Lo byte with
; %0000000000000000(Disable digital input buffers on all pins)
;(Register is %0000000000000000 out of reset)
#emac
#macro START_ATD0, 0
;*****************************************************************************************
;- Start ATD0 and get ADC values for all selected channels
;*****************************************************************************************
movb #$30,ATD0CTL5 ; Load ATD Control Register 5 with %00110000 (no special channel,continuous
; conversion, multi channel, initial channel 0)
; (Start conversion sequence)
; ^^^^^^^^
; SC-+||||||
; SCAN--+|||||
; MULT---+||||
; CD----+|||
; CC-----+||
; CB------+|
; CA-------+
;(Register is %00000000 out of reset)
brclr ATD0STAT0,SCF,* ; Loop here until Sequence Complete Flag is set
movb #SCF,ATD0STAT0 ; Set the Sequence Complete Flag of ATD Status Register 0 to clear the flag
ldd ATD0DR0H ; Load accumulator with value in ATD Ch00
std batAdc ; Copy to batAdc
ldd ATD0DR1H ; Load accumulator with value in ATD Ch01
std cltAdc ; Copy to cltAdc
ldd ATD0DR2H ; Load accumulator with value in ATD Ch02
std matAdc ; Copy to matAdc
ldd ATD0DR3H ; Load accumulator with value in ATD Ch03
std PAD03inAdc ; Copy to PAD03inAdc
ldd ATD0DR4H ; Load accumulator with value in ATD Ch04
std mapAdc ; Copy to mapAdc
ldd ATD0DR5H ; Load accumulator with value in ATD Ch05
std tpsADC ; Copy to tpsADC
ldd ATD0DR6H ; Load accumulator with value in ATD Ch06
std egoAdc1 ; Copy to egoAdc1
ldd ATD0DR7H ; Load accumulator with value in ATD Ch07
std baroAdc ; Copy to baroAdc
ldd ATD0DR8H ; Load accumulator with value in ATD Ch08
std eopAdc ; Copy to eopAdc
ldd ATD0DR9H ; Load accumulator with value in ATD Ch09
std efpAdc ; Copy to efpAdc
ldd ATD0DR10H ; Load accumulator with value in ATD Ch10
std itrmAdc ; Copy to itrmAdc
ldd ATD0DR11H ; Load accumulator with value in ATD Ch11
std ftrmAdc ; Copy to ftrmAdc
ldd ATD0DR12H ; Load accumulator with value in ATD Ch12
std egoAdc2 ; Copy to egoAdc2
#emac
#macro RUN_ATD0, 0
brclr ATD0STAT0,SCF,NoSeqCmplt ; If the Sequence Cpmplet Flag is not set, branch to
; NoSeqCmplt:
movb #SCF,ATD0STAT0 ; Set the Sequence Complete Flag of ATD0STAT0 to clear the flag
ldd ATD0DR0H ; Load accumulator with value in ATD Ch00
std batAdc ; Copy to batAdc
ldd ATD0DR1H ; Load accumulator with value in ATD Ch01
std cltAdc ; Copy to cltAdc
ldd ATD0DR2H ; Load accumulator with value in ATD Ch02
std matAdc ; Copy to matAdc
ldd ATD0DR3H ; Load accumulator with value in ATD Ch03
std PAD03inAdc ; Copy to PAD03inAdc
ldd ATD0DR4H ; Load accumulator with value in ATD Ch04
std mapAdc ; Copy to mapAdc
ldd ATD0DR5H ; Load accumulator with value in ATD Ch05
std tpsAdc ; Copy to tpsAdc
ldd ATD0DR6H ; Load accumulator with value in ATD Ch06
std egoAdc1 ; Copy to egoAdc1
ldd ATD0DR7H ; Load accumulator with value in ATD Ch07
std baroAdc ; Copy to baroAdc
ldd ATD0DR8H ; Load accumulator with value in ATD Ch08
std eopAdc ; Copy to eopAdc
ldd ATD0DR9H ; Load accumulator with value in ATD Ch09
std efpAdc ; Copy to efpAdc
ldd ATD0DR10H ; Load accumulator with value in ATD Ch10
std itrmAdc ; Copy to itrmAdc
ldd ATD0DR11H ; Load accumulator with value in ATD Ch11
std ftrmAdc ; Copy to ftrmAdc
ldd ATD0DR12H ; Load accumulator with value in ATD Ch12
std egoAdc2 ; Copy to egoAdc2
NoSeqCmplt:
#emac