MC9S12XE-Extended Memo.

[efoda]

Dear all,

I'm making something similar to E-Dictionary for a foreign language

the size of the dictionary file is about 4MB.

I use MC9S12XEP100RMW 

1.how can I distribute or scatter that file over the memo. of the MCU, any suggestions please?

(note: what I understood from MCU data sheet that allowed extended memory is only 2.75MB.

But CPU has 8MB global, so I need to divide the file between the CPU memo and extended, please correct me if I'm wrong)

2.what is the IC no. of EEPROM that can give me max. available memo. space

3.would it work if I used a larger EEPROM (about 3 MB) as I'm not sure to find one of exact 2.75MB

4.Do I have to write method to convert from that language to HEX & vice versa, if yes then, I think I won't apply this on the file parts that would be saved on CPU, it would be applied only on the file parts saved on extended memo., right?

Any tutorials or code or step by step instructions about this topic would be highly appreciated, I'm completely lost in this area!!

waiting your replies,

Thanks in advance,

Engy

[kef]

1. No. Allowed extended memory is 8MB minus size of on chip resources (registers, RAM, flash, EEPROM). 

Using CS0 chip select you can interface 3MB of memory at 0x400000-0x6FFFFF. Using CS1 - another 2MB at 0x200000-0x3FFFFF. Etc

2. I don't know. Ones with 16bits data bus are highly recommended.

3. I doubt there are chips with size other than power of two. Yes, you can use bigger chips.

4. It is not clear what you are talking about. Are you asking how to program your dictionary to external memory? Yes, you should do that somehow. Codewarrior won't do it for you since it doesn't know anything about your external memory and how it will be wired.

[efoda]

Thank you Kef v.v.v.v.much for your reply

but I wish you don't mind I still have questions:

forgive me but I'm still beginner

1.I'll buy EPROM and its burner then I'll use its procedure to put on it the dictionary data, how the MCU will c it in the addresses mentioned in the memory map and auto. divide it to 4 chips??

2.to access data/external memory, use GPAGE register only, right?

3. I was planning to put the code on the FLASH of the MCU, and the data on the external memory then the ROMON=0, right?

4.if I want to make something like bookmark, where the address of the last word displayed would be saved and displayed on the next time the device turned on, should I use EPAGE register and save that address in EEPROM 265KB area from 10_0000 to 14_0000, right?

Thank you for you time

[kef]

1. MCU can't autodivide external memory space among memory devices. Having more than 1 device requires chip select signal for each device. If existing 4 CS0-CS3 chip select pins are not enough, then you may generate additional chip selects using some simple logic, like active when CSn is active and some higher order address line An is active. Say you want 4x 64k chips in CS0 address space. You do circuit with 4 outputs. 1st output and chip select for 1st chip is active when CS0 is active and A17=0 and A18=0. 2nd output active when CS0 active and A17=1, A18=0. 3rd - CS0 and A17=0, A18=1. 4th - CS0 and A17=1, A18=1.

2. External memory is accessible not only using global addressing (GPAGE + Gxxx opcode). For example you can access internal RAM and all CS3 memory via RPAGE memory window. Part of CS2 memory can be accessed via EPAGE window. All CS0 memory - via PPAGE window. CS0 memory can be used to store banked program code. Part of CS2 or CS3 on some derivatives can be mapped to nonbanked 0x4000-0x7FFF.

3. I think Internal memory should be used, even if you have plenty of external memory. Of course if you find it simplier, then you can disable internl memory and run from external memory.

4. Yes, you can save such information to EEPROM.

[efoda]

Thanks Kef v.v.v. .. much for your help, I'm really grateful

about point 1, I was not planning to use more than 1 device, I thought to use 1 memory chip of 4MB for ex., and I was wondering how the MCU will know for ex.:

assuming FLASH_LOW address is $6F_FFFF then CS0 ranges from ($6F_FFFF-$3F_FFFF) corresponds to the address range ($0000 -$30_0000) on the memory chip 

CS1($1F_FFFF-$3F_FFFF) corresponds to addresses ($30_0000-$50_0000) and so on

or as I understood from your description above I should use 4 memory external chips that each would be connected to chip line select?

About point 4:writing to internal EEPROM:

I tried several times but none of my code worked:

I just want to save the chapter no. and the word no. to load them again on next power on or on specific interrupt

I write ANSI C in Codewarrior IDE

I wish you can help me in this

//first trial

extern volatile EPAGESTR _EPAGE @0x0800;

EPAGE=chapter_no;

extern volatile EPAGESTR _EPAGE @0x0802;

EPAGE=word_no;

//2nd trial

asm{

 EPAGE=chapter_no 

ld &EPAGE,#0x0802 

EPAGE=word_no

 } 
 //3rd trial

EPAGE=chapter_no;

address_of_EPROM=&EPAGE;

address_of_EPROM+2; 

&EPAGE+2; 

EPAGE=word_no;    

Thanks in advance for your time and effort

[kef]

Regarding EEPROM. Almost every EEPROM requires special programming sequence. Writing to EEPROM like to RAM is possible on S12XE. You only need to partiion DFLASH once. Since then you will only need on every MCU reset to properly setup FCLKDIV register and enable emulated EEPROM, EEPROM will be writeable like RAM. Check application notes AN3490 and AN3743:

http://cache.freescale.com/files/microcontrollers/doc/app_note/AN3490.pdf

http://cache.freescale.com/files/microcontrollers/doc/app_note/AN3743.pdf

http://cache.freescale.com/files/microcontrollers/doc/app_note/AN3743SW.zip

[kef]

Single memory chip is even more easier. You don't need any chip select. CS input pin of memory chip can be simply shorted to 0V.

I don't know if this will answer your question, but MCU has some address decoding logics. It knows that from and above 0x700000'G there's internal flash. While internal flash is enabled, accesses above 0x700000'G won't produce any activity on external memory bus. All accesses to address, not occupied with internal RAM/FLASH etc, are directed to external memory bus.

Just connect RAM/ROM as follows:

all MCU DATA0-DATA15 pins - to RAM/ROM D0-D15

                        - RAM/ROM CE\ to 0V.

WE\                  - WE\

UDS\/ADDR0 - UB\

RE\                   - OE\

LDS\                 - LB\

ADDR1-ADDR21   - A0-A20

Then you start as usual in single chip mode, setup external bus registers and switch to Normal Expanded mode like this:

{

   EBICTL0 =   EBICTL0_ITHRS_MASK*0
             | EBICTL0_HDBE_MASK
             | (21+1);                // Enable address lines A0 to A21

   
   MODE =   MODE_MODC_MASK*1      // switch to NE mode
          | MODE_MODB_MASK*0
          | MODE_MODA_MASK*1 ;

}

After executing this code all external memory accesses (accesses to space not occupied with registers 0-0x7FF, internal RAM, internal FLASH etc) will be directed to your memory chip.

Regarding burning external EEPROM in memory burner. Since there's no free 4M aligned 4M memory hole, you need to tell your burner to shift starting address. Available on S12XE memory hole is from 140000'G to 0x6FFFFF'G. You could map ROM just below internal flash, from 0x300000'G tp 0x6FFFFF'G. Then you need to burner to start burning not from ROM intenal address 0, but from 0x100000. I hope it's clear? What burner programs to 0 in ROM, you will see at 0x400000'G, 0x100000->0x500000'G, 0x200000->0x600000'G, 0x300000->0x300000'G.