I ported from a MC9S12A256CPVE to MC9S12XA256CAL Freescale processor. I am having trouble with accessing the 4k EEPROM space. I realize the EEPROM operation is different for both processors.
The NVRAM (EEPROM) drivers for the MC9S12A256CPVE are based on AN2400. I am using these same drivers on the MC9S12XA256CAL. They work for EEPROM addresses 0x0800 to 0x0FF0. I am not sure about the other 2k of EEPROM.
To verify that my old code was working ok on the new processor, I configured an S19 File write in two 2032-byte NVRAM images at physical locations 0x13F000 (base address 0x????) and 0x13F800 (base address 0x0800). These are byte addressable. The maps are identical.
I am able to read locations 0x0800-0x0FF0 and verify against a hardcoded map to make sure the stored contents match what I expect to be there.
For the second map, I am unsure as to where it lives and if I have to manipulate the EPAGE register to access the other 2k?
The PRM file is as follows:
EEPROM = READ_WRITE DATA_NEAR IBCC_NEAR 0x0C00 TO 0x0FFB;
EEPROM_FC = READ_WRITE DATA_FAR IBCC_FAR 0xFC0800 TO 0xFC0BFF;
EEPROM_FD = READ_WRITE DATA_FAR IBCC_FAR 0xFD0800 TO 0xFD0BFF;
EEPROM_FE = READ_WRITE DATA_FAR IBCC_FAR 0xFE0800 TO 0xFE0BFF;
//EEPROM_FF = READ_WRITE DATA_FAR IBCC_FAR 0xFF0800 TO 0xFF0BFF;
Is there a good App Note that will help clear up this confusion or is there a sample project that shows how to use the 4k EEPROM?
Any assistance is greatly appreciated.
Ok, I figured this out via testing and reading all the other positings on this subject. I need clarification on one item.
Referring to the .prm entries on my original post, Is EEPROM (which is the same as EEPROM_FF) always mapped to 0x0C00 in the local map regardless of what EPAGE is set to?
It would seem then if I set EPAGE to 0xFF, then 0x0800 to 0x0BFF is mirrored at 0x0C00 to 0X0FFB (not taking into consideration that from 0x0FFB to 0xFFF are protected areas according to the datasheet). Can anyone please confirm?