MC9S12DJ256 - Reset asserted low at power-up

[RumJungle]

Hello Group,

I'm the software guy working on a new board and the hardware guy is telling me that this is a software problem. I'll help him in his quest.

We have built a few prototype boards (10) and six of them cannot communicate with the BDM. The other four do. I've check that there is a clock and that there are no shorts. The strange thing is that the reset seems to be asserted low and stays there on some boards.

1. Why would the CPU reset pin be asserted low and stay there?

2. The BDM claims that there is no clock or it is not connected to the CPU. What are some of the items I should be looking for to figure out why the BDM does not communicate?

Thanks for your help.

[RumJungle]

Yes, I'm confident it is an manufacturing assembly problem or maybe a HW design problem. However, like always, I will have to prove it is not software and find the problem. So...

If the BDM does not communicate, what are some of the items that I should look for?

   * Clock

   * Power

   * Reset

   * Other items.

I don't get much help from hardwaer so any constructive answer would be appreciated.

TIA

[JimDon]

Well, yes all of those.

Did you resolve the reset being stuck low?
That's a show stopper right there.

Check all the power pins.
Check that the oscillator runs. Do have a scope?

We can't look at it, so you will have to and tell us what you see.

[RumJungle]

Hi,

Thanks for the help.

Here is the scenario:

* Clock - 10MHz looks as if it is going to the CPU and good.

* Reset controller looks like it is working. Disconnect the CPU (lift pin) reset from the reset controller and you see the reset pulse at power-up from the reset controller. However, looking at the raw (disconnected) RESET pin on the CPU, it shows low. When the reset controller is connected to the CPU RESET pin, you can see that it is trying to reset the CPU. You can see very little change in the “low” state.

* Power pins looks good.

My only guess it that some of the CPU pins are not connected correctly or there may be missing connections. A little frustrating, but I am looking at the HW datasheet.

TIA

[kef]

Sounds like you are using external clock instead of crystal. Check the amplitude of this clock. It should be about ~2.5V (VDDPLL voltage), and not 5V. Also check the voltage at VDDPLL, VDD1 and VDD2. It should be close to ~2.5V. VDDPLL, VDD1 and VDD2 should be NOT connected to 5V.

Is there pull-up at /RESET pin?

VREGEN should be pulled up to 5V. VDDR, VDDA, VDDX - 5V power supply inputs.

MODA, MODB pulled low, BKGD pulled high, XCLKS pulled high or low depending on oscilator circuit, Pierce(or external clock) or Colpitts.

[RumJungle]

Hello All,

Thanks for your help. I was able to show the HW guy that he had the wrong voltage. He was trying to feed the CPU 3.5V where it should have been 5V. I think that this was the root of the problem. The datasheet showed a 4.5V minimum.

Again thanks for the help.

[JimDon]

Well, thank you for telling us the resolution.
I am amazed any of the boards worked like that.

[JimDon]

How did you determine that the reset pin is NOT shorted?
Your hardware guy DID put a reset generator chip on the board, right?

If 4 of them do work pretty hard to claim it is software.