MC9S12DG oscillator layout confusion

[jpurdom]

Hi!

I am working to re-layout one of our display cards due to interference issues. I have recently started working on the uP (MC9S12DG128). Reading through  the design guides I have run across conflicting guidelines on how to layout the oscillator circuit. In the uP datasheet and the original hardware design guide it says to leave an 'exclusion zone' under the osc section due to stray capacitance worries. However, in more recent docs (also for the same MC9S12 family) I have found it saying that running a gnd plane under the osc is not a problem and can even be advantageous in noisy environments.

Which guideline should I go with? This PCB is mounted in a very noisy environment.

Thanks!

[RadekS · Accepted solution]

I am afraid that for this topic you will never get “right” answer. Both solution has own advantages and disadvantages. I am not PCB layout expert but from my experience I know that there isn’t any strict rule, just few recommendations.

I would like recommend an 'exclusion zone' under the oscillator section. Of course, the main recommendation is to leave the oscillator section as smallest as possible and as close to the MCU.

If you choose GND plane under oscillator section (crystal, capacitors, PLL filter), I would like recommend create here separate GND area which is connected to main GND plane just in one point = at  VSSPLL pin. If you use for example four layer PCB, this GND area should be presented on all layers (areas are connected by via holes).