MC9S12A64 Power Supply

[TechnoSage]

I'm having trouble making head or tail of the datasheets with regards to supplying power to an S12A64CPVE chip. I've used the 'proposed layout' for a Colpitts oscillator on an 112-LQFP part, but I'm unsure as to levels to be supplied to each supply pair and what's connected internally - either to the on-chip regulator or by metal inside the part. I'm wanting to supply with 5V, use 2 ATD pins, 2 PWM pins and not bother with the PLL or digital logic.

I've included 2 screenshots - hopefully they give enough detail. The board isn't complicated in the slightest - I just don't want to have a PCB made, discover it's wrong and potentially break a uC.

Thanks for any help

[kef]

I recommend to avoid using Colpitts oscilator.

In DJ64 Device User Guide see Table 2-2. 2.5V voltages VDD1, VDD2 and VDDPLL are generated by onchip voltage regulator. You may also check block diagram. Power pins arrows that are pointing to the chip are external supplies. Power pins that are pointing to the outside of chip are intenal supplies generated by onchip voltage regulator. You need to decouple these pins with capacitors. Required capacitances are specified in datasheets. You need to GND all VSS? pins and VSSPLL.

Though you may not like PLL, but you should install proper PLL filter circuit. In case crystal oscilator fails, availability of PLL filter will allow MCU to operate at self clock frequency and allow you to detect oscilator failure and light some error LED or something like that.

Your diagram is not very readable. You need at least to stretch A64 symbol a bit, to make pin names readable.

Voltage supervisor (brown out detector) at RESET pin is missing. You need it for normal operation of these old S12D/S12A devices. Unlike more modern S12(X), S12A doesn't have built in LVD (low voltage detect) and you need external one.

You forgot to GND TEST pin.

MODA, MODB should be tied low for special single chip mode. XCLKS pin should be pulled up for Collpits and low for Pierce.

[TechnoSage]

Thanks for the advice - I really appreciate it!

I think I may have misunderstood you regarding the supervisor and PLL stuff (the circuitry around the PLL pins is from the manual), but I have included an LT chip for brownout detection and fixed a few things as you suggested. I have also increased the size of the chip so that reading it is a lot simpler; Cadence didn't like the fact I changed the size, didn't fix the connections and wouldn't let me change it, so I've had to redo the whole board, but hopefully this time it's nearer to being ready.

Again, I have included screenshots to display what I've done. I hope this is better.

Thanks again for your time and your help.

TS

[kef]

ADM6305 has either 1.23V or 0.4V threshold voltages for input pins and doesn't monitor Vcc. You need voltage divider at one of inputs to shift threshold up to 4.5V (specified Vdd5 minimum for S12A64). Alternatively you switch to ADM6306, with an option of 4.5V Vcc threshold. 

You need pull up resistor at reset pin, like 4k7

You need decoupling capacitors between VDD1-VCC1 and VDD2-VCC2. At least 100nF each.

VREGEN pin should be tied to VCC.

More decoupling at VCC won't make it worse. Should work.

(Indeed I would choose Pierce oscilator instead of Collpitts)

[TechnoSage]

Thanks for the changes.

I've put them in and taken your advice regarding the Pierce oscillator, although finding the component values was a litle tricky - there appears to be information missing from Freescale datasheets that would be quite useful.

Again, I've added screenshots of the schematic, hopefully it'll be perfect this time (I added the 4.5V threshold on the supervisor, by means of a voltage divider as you suggested, put in the 4k7 res. on RESET and fixed the VDDx, VSSx and VREGEN mistakes).

Thanks again for all you help!!

[kef]

You are dividing 5V Vcc down to 4.5V. But you need to divide 4.5V to get ADM6305 threshold voltage. When Vcc drops below 4.5V you need to have 1.25V  or 0.4V at ADM6305 input, depending on exact ADM6305 part number. Look in datasheet for differences Z vs Z1.

[TechnoSage]

Thanks for the heads-up. I misunderstood the datasheet - I'll swap the divider for a 20.5K (in place of the 1K) with a 2K (in place of the 9K) to get 0.4V into the pin when VCC drops to 4.5V. I hope this solves that problem.

Does that cover all the issues you can see with my design?

Thanks again for all your help - I really appreciate it and understand that my lack of experience with the device must have made my questions frustrating, for which I can only apologise. 

[kef]

• Does that cover all the issues you can see with my design?

Yes, at least obvious ones, which would make PCB useless. 

[MJW]

Hello,

IMHO there is another issue with the schematics: there is a connection between VDDR and VDDPLL.

I think this is wrong, VDDPLL belongs to the 2.5V domain, i.e. is on the output side of the VREG while VDDR is the input of the VREG.

Also, the Ground connection for the TEST pin is missing.

MJW

[kef]

Right. It was fixed in older version.

[MJW]

One more thing:

It is not really obvious from the schematic if this a problem (H-BRIDGE CONTROLLER?), but please be aware that the PAD pins on most S12D/S12A family devices cannot be used as outputs.

MJW

[TechnoSage]

Thanks for all the help.

The VCC connection between VDDPLL and VDDR should not be there and I didn't notice it, so I've fixed it. When I changed the size of the uC to make it more readable Cadence didn't like it so I had to redo the whole board and forgot to re-ground the TEST pin, that's fixed too. I've also moved the H-Bridge controller header over to PA7-PA3 - they are control lines for a MOSFET control chip,so they do need to be outputs.

Thanks again for all the advice.