MC9S12A128CPVE migration question

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MC9S12A128CPVE migration question

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mikepalmer
Contributor I

We use MC9S12A128CPVE [LQFP 112 package] in a legacy product and we are running out of flash and RAM space as we add new functionality.   The [1] MC9S12A256CPVE and [2] MC9S12A512CPVE appear to have identical footprint.   Could [1] or [2] simply be mounted in place of the MC9S12A128CPVE on our legacy product, with no changes in existing binary code and no other circuit board changes, to provide a quick forward path for extending development?   It *seems* like they'd be identical, but I haven't seen specifics anywhere.   I was concerned about such things as, for example, [a] the 256 part seems to have 91 GPIOs, not 59, and [b] if the flash size changes, might the flash sector sizes change such that an erase sector command erases a different amount of mem on different chips..   Thanks in advance.

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Lundin
Senior Contributor IV

Yes they are fully compatible, assuming you don't end up with very old silicon masks, in which case S12x256 parts may be more buggy than others, because they were released first. I doubt this will be an issue though. x256 is a super-set of x128.

If you want to take advantage of the additional RAM and flash, then you'll naturally have to make changes to the binary:

- You need to change the linker script to correspond to the larger memory map. In Codewarrior this is done by changing the .prm file.

- You have to set the INITRM and INITEE registers to correspond to the larger memory map.

- You have to adjust the stack pointer and possibly also the stack size. I would strongly recommend placing the stack at the beginning of the RAM, so that in case of stack overflow, the program will merely attempt to overwrite read-only EEPROM memory, instead of going Toyota all over the RAM.

As for GPIOs, every S12 has the same amount, given that it has the same amount of pins. You have around 70 GPIO pins on a QFP112, no matter memory size. On top of that you have 8 or 16 input-only pins, depending on whether there is one or two ADCs. Not sure where you have heard any other figures.

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Lundin
Senior Contributor IV

Yes they are fully compatible, assuming you don't end up with very old silicon masks, in which case S12x256 parts may be more buggy than others, because they were released first. I doubt this will be an issue though. x256 is a super-set of x128.

If you want to take advantage of the additional RAM and flash, then you'll naturally have to make changes to the binary:

- You need to change the linker script to correspond to the larger memory map. In Codewarrior this is done by changing the .prm file.

- You have to set the INITRM and INITEE registers to correspond to the larger memory map.

- You have to adjust the stack pointer and possibly also the stack size. I would strongly recommend placing the stack at the beginning of the RAM, so that in case of stack overflow, the program will merely attempt to overwrite read-only EEPROM memory, instead of going Toyota all over the RAM.

As for GPIOs, every S12 has the same amount, given that it has the same amount of pins. You have around 70 GPIO pins on a QFP112, no matter memory size. On top of that you have 8 or 16 input-only pins, depending on whether there is one or two ADCs. Not sure where you have heard any other figures.

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mikepalmer
Contributor I

Thanks much for the detailed response and advise, Daniel!

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