Low voltage rest problem - MC9S12XDP512

[Filip_83]

Hi, I have MC9S12XDP512 in my project. When using the pseudo stop mode and the PLL, bus frequency 40MHz, because of time demanding calculations, the instrument accidentally restarts, after about hours. After the reset, the register CRGFLG contains the value 60 decimal, which means a low voltage reset. If I use WAI mode and not use PLL, the problem does not occur. Can you give me an advice? Thank you.

Added p/n to subject.

Message Edited by NLFSJ on 2008-04-11 09:55 AM

[DPB]

Hello
"CRGFLG contains the value 60 decimal" equates to 3C hex. Thus LVRF is set but PORF is clear.

LVR monitors VDD in VREG full power mode only. In (pseudo) STOP mode the VREG is in reduced power mode (RPM). Thus the LVRF bit is set either before entering (pseudo) STOP mode or after exiting (pseudo) STOP mode. In WAIT mode the VREG stays in full power mode.

This looks like a power moding problem, since the problem does not occur when using WAI without PLL.
To prove this you could use WAI and still use the PLL. If it is a power moding issue, then the problem should not occur with this configuration.

To avoid power moding problems ensure that you use the VREG capacitive loads given in S12XDP512 ref.manual Table A-20. Also ensure that you have no external loads on VDD and ensure the integrity of the VDDR and VDDA pins when entering STOP.  Note that VDDA is also used as VREG supply and must stay in the specified range to ensure VREG functionality and prevent LVRs

This could also be related to errata MUCts03646: If a wake up from (pseudo) STOP is requested within a specific very short window (typically 11ns long, not longer than 20ns) within 1.6 and 4.7us after entering STOP then  a reset is generated and the LVRF is set. The window of occurrance is very small, so the
probability of this happening is very small, but it could in possibly explain the problem if power moding issues can be ruled out.

DPB