Interrupt stacking order for MC9S12XD64?

[usdkurt]

Hi, I'm using the MC9S12XD64, and I'm finding a descrepancy in the documentation.  The MC9S12XDP512 reference manual supposedly applies to this chip; on page 608 section 16.4.2.1 it refers to the interrupt priority level being part of the CCR and being stacked as part of the interrupt context save.  However, the CCR normally occupies a full byte already for the SXHINZVC bits, so this implies that a 16 bit CCR is being stacked.

This same chip references the  S12CPUV2.pdf as the CPU reference manual.  On page 321 it lists the stacking order for the CPU12; the CCR is shown as a byte only, stacked at SP+0.

My guess is that the interrupt priority level is stacked at SP+0, and the other registers each get bumped up by a byte, such that 

SP+8 => return address

SP+6 => Y register

SP+4 => X register

SP+2 => B:A

SP+1 => CCR

SP+0 => IPL

Does this seem like the right interpretation?

Kurt

[CompilerGuru]

Lookup the S12X reference manual, "S12XCPUV2 Reference Manual" not the S12 one.

The S12 family does have a 8 bit codition code, for the S12X a CCRH was added which contains the IPL.

http://www.freescale.com/files/microcontrollers/doc/ref_manual/S12XCPUV2.pdf

If the MC9S12XDP512 manuals refer to the S12CPUV2 (note no X) manuals, then that is a single character bug in those manuals, please report it (via service request) so it gets fixed in upcoming manual releases.

Daniel

[usdkurt]

Daniel, thank you for helping me.  I suspect that it was my own error in downloading the incorrect CPU manual - I thought I had gotten it from the product page, but when I check the product page I see that the correct version is linked there.

Kurt