IIC lose arbitration result of SDA bus lock

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IIC lose arbitration result of SDA bus lock

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Xuqq
Contributor II

When we are doing IIC error monitor. Our test method is to manually connect the SDA bus to GND, and then the IIC error is detected. When the SDA bus is disconnected from GND, the SDA bus should return to normal and the error disappears. But we found that sometimes the SDA bus line cannot be restored to high.

We used the hardware IIC of the S12ZVL96 microcontroller, and it is master, another MCU as a slave. 

Master send data 0x20 and 0x40, In the figure below, we can see that the master has normally sent 0x20 and received the ACK from the slave. When the master sends 0x40, the SDA line is manually connected to GND, that is, the SDA line at  A  in the figure is manually connected to GND. At this time,the microcontroller should be lose arbitration.We read the IBAL register and it has been set. S12ZVL96 should be switched to slave mode.In the picture, you can see that the 9th clock has not been sent to completion before switching to the slave mode. It will cause the slave to not release the SDA bus after acknowledging the ACK. After this, we manually disconnect the link between SDA and GND, and we will find that SDA is low, the master cannot control the bus.  

If I don’t reset IIC, is there any other solution?  And I think master should send the ninth clock before switching to the slave. Why does the problem at B in the figure appear? 

I1.jpg

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13 Replies

2,766 Views
Xuqq
Contributor II

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2,781 Views
danielmartynek
NXP TechSupport
NXP TechSupport

Hello @Xuqq,

I understand it is the slave device that is holding the SDA line low.

If so, according to UM10204I2C-bus specification and user manual, the Master should send 9 clock pulses to release the line.

danielmartynek_0-1638521786189.png

https://www.nxp.com/docs/en/user-guide/UM10204.pdf

 

Regarding the ACK clock cycle, the ACK signal is tested during the HIGH period of this clock pulse.

So, the cycle is there.

 

Regards,

Daniel

 

 

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2,760 Views
Xuqq
Contributor II

Hello Daniel

    Thanks for your reply.I have understood how to clear the bus. I also want to know what are the reasons for generating an incomplete ninth clock by the S12ZVL96 at B in the figure?

     Because I understand that the SDA bus should not be released by the slave until it detects the falling edge of the ninth clock.And the falling edge of the ninth clock generated by s12zvl96 is incomplete, the slave may not know that this is a falling edge.In this way,the slave should not release the SDA bus.

Regards,

Xu

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello Xu,

 

What is the sampling frequency of the oscilloscope?

And what is the bus capacitance?

danielmartynek_2-1638544329045.png

 

Anyway, according to the specification, the Master that loses arbitration can generate the clock to complete the byte but without the stop condition.

And there seems to be no specification on how long the Master should hold the SCL low after the 9th bit.

danielmartynek_0-1638543193825.pngdanielmartynek_1-1638543241626.png

Basically, every transfer must end with the a Stop condition.

danielmartynek_4-1638544979179.png

 

So, even if the Master held the SCL line low for a while, the Slave would still consider the bus to be busy.

 

Regards,

Daniel

 

 

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Xuqq
Contributor II

Hello Daniel,
    I'm really sorry to trouble you all the time. The bus capacitance is 100pf

‘even if the Master held the SCL line low for a while, the Slave would still consider the bus to be busy’  I think you are right. However, I think even if the slave does not receive a stop signal, it should release the SDA bus after it detects a valid falling edge of the ninth clock. Because after receiving the valid falling edge of ninth clock,this is, after repling to the ACK, the slave needs to release the SDA bus and wait for the valid data from the master. So  when the master lose arbitration, if there is a valid falling edge of the ninth clock, the SDA bus will not hold low by the slave.

Anyway, thank you very much for telling me how to clear the bus. In additon, after many tests, there is no complete falling edge of the ninth clock when the master lose arbitration. Is it the characteristic of s12zvl96 chip?

Regards,

Xu

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello Xu,

This is the first time I hear about this kind of issue.

 

The IIC module is rather simple and not very flexible.

The only thing we can adjust is the IIC Frequency Divider Register (IBFD).

 

Do you see IBSR_TCF = 1 after the transfer?

 

Possible workaround could be in disabling the IIC module (IBEN = 0).

The ports will then switch to a function with a lower priority:

danielmartynek_0-1638870194839.png

If TIM0 is disabled, the ports will be routed to GPIOs.

And if PTT1 = 0, SCL will be driven to LOW at the time the IIC module gets disabled.

 

Regards,

Daniel

 

 

 

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2,681 Views
Xuqq
Contributor II


Hello Daniel,
      I can confirm that the SCL signal,the SDA signal,TCF register, etc. are correct when the IIC communication is normal. But when a master loses arbitration, the falling edge of the 9th clock of the last byte will appear incomplete.
       I have a new test about master lose arbitration, the rate of IIC is 100Kbit/s,the real-time sampling rate of oscilloscope is about 3.125MS/s. Master is S12ZVL96,and the slave is another microcontroller.There are two test pins,one is TestPin-TCF, this pin will become low when TCF register is set to 1 after the start signal. The other pin is TestPin-IBAL, it will become low when IBAL regeister is set to 1. Let's look at the picture below, the data is sent from the master to the slave, it should be 0x21. Because I manually connected SDA bus to GND near point A,the SDA bus data became 0x20. In this way, the S12ZVL96 should think that there are other masters occupying the SDA bus,and it should lose arbitration.IBAL register is set to 1,but the TCF register is not set to 1. 

1.png

First, regarding the ICF register is not set to 1,the IBAL register is set to 1,I think it is right. The master lose arbitration, so the IBAL register is set to 1. When the master loses arbitration, the master immediately switches to the slave, according to the conditions of IBAL set, I think IBAL register will not be set to 1 at this time.

2.png

3.png

Then, I think the S12ZVL96 already knows that it has finished sending a falling edge of the 9th clock. Otherwise,it will not generate an interrupt and will not set IBAL to 1. Since the register of S12ZVL96 shows that the falling edge of the 9th clock has been generated, but what is actually measured by the oscilloscope is an incomplete falling edge of the 9th clock. If the hardware design has a bug or the oscilloscope measurement has an error, this incomplete falling edge should not appear at this moment,it should be found randomly or in every byte. So I suspect it is very likely that it is the S12ZVL96's characteristic.4.png

Regards,

Xu

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello Xu,

Thank you for the additional information.

Let me trigger an internal discussion whether this is intended behavior or not from design point of view.

But anyway, I don't think there much we can do with this.

What about switching the IIC module off so that the SCL pin can become a GPIO output and be driven LOW once the IBAL interrupt is called.

I think this would be a possible solution to have the 9th falling edge there.

 

Regards,

Daniel

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Xuqq
Contributor II

Hello Daniel,

      I will try to slove this problem in some ways, and I look forward to the resolution you discussed.

Regards,

Xu

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello @Xuqq,

I'm sorry for the delay.

We have been tryting to reproduce it but without any success.

For example: PS0 wired-or output driven low within the IIC frame, PJ0 SDA, PJ1 SCL

PS0 - PJ0 disconnected:

danielmartynek_0-1644583630158.png

The last SCL low period is always longer than what you reported.

Can you please share the project?

Or at least BUS clock frequency and the IBFD configuration?

 

Thank you,

BR, Daniel

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2,139 Views
Xuqq
Contributor II

Hello Daniel,

    Thanks for your reply.

     The following is the hardware schematic diagram.

Hardware.png

    The bus clock frequency is 100k Hz. The registers before enabling IIC are configured as  follows:

     IIC0IBSR = 0x12;    IIC0IBFD = 0x1D;    IIC0IBCR2 = 0x00;

     IIC0IBAD = 0x00;    IIC0IBCR = 0x00;    IIC0IBCR |= 0x80;

 

     In additon, I didn't find any problems in your test. Due to the diversity of test environments, in order to ensure the consistency of problems, I hope to add a test pin about register IBAL in your test environment, or monitor the IBAL register. In the above test environment, if the IBAL register is set, it can be confirmed that your operation causes the host to lose arbitration. Otherwise, we don't know whether the host has lost arbitration.

Regards,

Xu

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danielmartynek
NXP TechSupport
NXP TechSupport

Hello @Xuqq,

Thank you for all the information.

I have been trying to reproduce it again.

And I can confirm the IBAL bit get set in my tests.

 

What I found that the LOW PERIOD after the 9th pulse does not depend on the selected IIC Baud rate but on the selected BUS_CLK frequency.

At 6.25MHz BUS_CLK, it is driven LOW for 0.85us

danielmartynek_0-1645547397709.png

At 16MHz BUS_CLK, 0.37us

danielmartynek_1-1645547457589.png

Which is ~5 BUS_CLK cycles.

So, I assume you must use a higher BUS_CLK frequency.

 

But anyway, it is driven all the way down.

I think the issue is in the bus load.

Can you remove the additional 470R / 100pF load?

 

Best regards,

Daniel

 

 

 

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1,811 Views
Xuqq
Contributor II

Hello Daniel,

      I've been busy recently. I'm very sorry for the late reply.

     The system clock frequency is16 MHz. I will try to remove the additional 470R / 100pF load for testing.

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