Hi,
I am trying to test memory corruption in the Flash module ECC of MC9S12G. I have the following questions on how the ECC works in here:
1. If we force a single bit or a double bit error through FCNFG register, how does it really test that the ECC works correctly when the actual bit errors occur?
I feel that it just set the flags for the interrupts to fire, Is my understanding correct?
2. How can i create/simulate single/double bit faults to test the ECC functionality?
Also, Is there any other way in MC9S12G micro to check for memory corruption(Flash area)?
Thanks in advance,
Firoz
已解决! 转到解答。
Firoz,
You assumptions regarding setting the FDFD or FSFD bits in the FCNFG register is correct. It does not generate an actual ECC error but only allows you to check the error handler ISR for ECC errors.
At one time I inquired of the designers as to how to purposely generate ECC errors for other 0.18u S12/S12X devices. The only way is to over program a phrase of Flash data with new/different values. While this goes against the specification (a phrase of Flash must be erased before it can be programmed), it would be useful for testing. Over programming a phrase will cause the ECC to be reprogrammed with a new value along with the phrase data. However, you may have to try over programming a single phrase more than once to get an ECC error. It just might be that the new ECC syndrome will be correct for the new phrase.
Again, reprogramming an already programmed phrase without first erasing it goes against the specification and should only be done for testing. Not in production code.
Hope this helps.
Regards,
Gordon
Hello Radek,
This example works very well in Flash, but not in EEPROM what is logical because I guess the ECC codes are not computed the same way. Would you also have the datas that should be written in EEPROM to generate a single or double ECC errors ?
Thanks
Hi Yves,
You are right, the EEPROM use different 22bit ECC scheme (16bit data + 6bit ECC).
I prepared for you a simple example code which simulates and highlights ECC errors by cumulative write into EEPROM.
S12Z - Simulating ECC errors at EEPROM by cumulative write
The previous example code for ECC at Flash is published at:
S12Z - Simulating ECC errors at Flash by cumulative write
The example code for simulating ECC errors at RAM is published at:
https://community.nxp.com/docs/DOC-334328
In the case of any issues, please let me know.
I hope it helps you.
Have a great day,
Radek
Firoz,
You assumptions regarding setting the FDFD or FSFD bits in the FCNFG register is correct. It does not generate an actual ECC error but only allows you to check the error handler ISR for ECC errors.
At one time I inquired of the designers as to how to purposely generate ECC errors for other 0.18u S12/S12X devices. The only way is to over program a phrase of Flash data with new/different values. While this goes against the specification (a phrase of Flash must be erased before it can be programmed), it would be useful for testing. Over programming a phrase will cause the ECC to be reprogrammed with a new value along with the phrase data. However, you may have to try over programming a single phrase more than once to get an ECC error. It just might be that the new ECC syndrome will be correct for the new phrase.
Again, reprogramming an already programmed phrase without first erasing it goes against the specification and should only be done for testing. Not in production code.
Hope this helps.
Regards,
Gordon
Hello Gordon,
Do you know what sequence of write operations (and what data) should be written in Flash to generate a single or dual ECC error in flash ? (the device I consider is the S12ZVMC256).
Thanks
Yves