Currently, I am implementing the low voltage Interrupt for the S12ZVL chip. However, when I was trying to test it, I could not trigger the interrupt for LV. According to the datasheet, I have adjusted the supply voltage to the chip below 4.23V to trigger the LVI, but my debugger already lost the communication because of the low voltage. So the break point in LVI never got reached. Could you please share some idea to help me test the LVI?
this is similar like COP debugging.
You have to check behavior of the interrupt function in normal mode with correct voltage by some SW call/jump to the interrupt function or define the function as standard - non interrupt and debug it. It is suitable to add to the function a visual/communication/any flag, for example toggling pin or switching some diode or send serial data.
When the function is working in expected way in normal mode without interrupt you can then set everything for LVI test. Run the application code, initiate LVI condition and only check whether the function passed your visual/communication/any flag.
This is a indirect debugging but works without any issue.
Thank you for your response and suggestion, I am very appreciated.
I have checked my function in the LVI first, I toggled PT7 I/O port there, it works fine in normal mode.
Then I moved the function into LVI then test it, but it does not work.
Here is the question about initiate LVI condition, what I did is low down the power supply to chip lower than 4.23V, to see if the PT7 got toggled or not. But it does not toggle. Then I low down the power supply to chip lower than 4.23V then back to 7V, the pin still does not toggle.
I think the chip doesn't work or goes to stop mode if the supply voltage is below 5.8V. Could you please tell me what is the correct action to do if I want to initiate LVI condition?
I think that there is mainly misunderstanding in voltage measurement points.
The LVI is monitored on the VDDA supply domain. So, the LVI should occur when VDDA (must be externally connected with VDDX) voltage falls below 4.2V. Unfortunately, we cannot specify appropriate VSUP voltage since the voltage drop at internal LDO depends on load current, temperature, … But around 6V at VSUP sounds reasonable.
When you decrease VSUP at 4.23V, the voltage at VDDX will be already below low voltage reset value (around 3V).
Unfortunately, you didn’t specify which S12ZVL derivative you use. If you use S12ZVL128 (96/64), please be aware, that LVI is available only when VREG is configured to 5V (CPMUVREGCTL_VREG5VEN=1). In default case when VREG provides 3.3V, the LVI feature doesn’t have sense. The S12ZVL32 (16/8) derivatives have 5V voltage regulator only.
For enabling LVI, we must set CPMULVCTL_LVIE bit and clear I bit in CCR register (macro EnableInterrupts;).
Interrupt vector number: VectorNumber_Vlvi 62
Note: Be aware, that the LVI is disabled when MCU is in STOP mode.
If you want monitoring the VSUP voltage directly, you may enable Low Voltage Warning (BATS module) by BATE_BSUSE bit, select one of four low voltage levels (BATE_BVLS bits) and enable interrupt by BATIE_BVLIE bit.
Interrupt vector number: VectorNumber_Vbats 47
The third option for VSUP voltage monitoring is periodical ADC measurement at internal channels (VSUP BATS-Internal_4, HVI Port L0-Internal_5). Be aware, that appropriate module must be enabled and configured prior measurement start.
I hope it helps you.
Have a great day,
Thank you very much for the explanation and suggestions. Really in details, I do appreciate.
Here is what I can confirme:
1. We are using a chip S9ZVLA128, I checked the register for CPMUVREGCTL_VREG5VEN=1;
2. I have checked the register for CPMULVCTL_LVIE =1, but I didn't find how to "clear I bit in CCR register (macro EnableInterrupts)", please let me know how to do it if you think it is necessary to clear this register;
3. I can also confirm the LVI vector address is 0x00FE0104, which is the same as the datasheet specifies;
4. I have enabled the BATS module and used ADC to sample the internal channel for Vsup, my BATS interrupt can be triggered at Voltage level VLBI1 when Vsup is around 5.6V, which I could know the chip could work at that voltage level.
This is what I don't understand, please let me know if you have any suggestion:
1. I took a measurement on the Vsup, VDDA and VDDX pin of the chip:
when Vsup is around 6V, the VDDA and VDDX are 5.08V, which will not trigger the LVI;
when Vsup is 4.23V, the VDDA and VDDX are also 4.23V, which shall trigger the LVI but didn't;
But it is different according to what you tell me that "But around 6V at VSUP sounds reasonable. When you decrease VSUP at 4.23V, the voltage at VDDX will be already below low voltage reset value (around 3V). "
2. I am thinking the way to decrease the voltage on VDDA is not effective, so I short-circuit the VDDA with VSSA since those two pins are next to each other, but the LVI still didn't trigger, the toggle pin I put in the interrupt is not working. So could you please let me know if there is any other way you guys test the LVI?
clears the I-bit in CCR register. This globally enables all enabled I-bit maskable interrupts.
It is a simple macro (in hidef.h file) which executes assembler CLI instruction (__asm (CLI);).
The same voltage 4.23V at VSUP and VDDX sounds strange. It looks like the voltage regulator does not work correctly. Could you please share your schematic? If the schematic cannot be shared here as public, please create a ticket and attach it for a short review.
Unfortunately, the testing via power supply short isn’t the best way how to test the low voltage interrupt. The short between VSSA and VDDA will cause the low voltage reset trigger before low voltage interrupt routine may be reached.
The correct way how to test LVI is slow decreasing VSUP power supply and watch the VDDA voltage. If you use an oscilloscope, also the reset signal may be useful to display.
Idea: If you want test LVI without the influence of internal regulator, you may set up 5V at your power supply, then temporary short VSUP and VDDX (internal regulator bypass), connect the board to the power supply and slowly decrease the VSUP(=VDDX=VDDA) voltage. Be aware, that you cannot go back with VDDX/VDDA higher than 6V – that may cause permanent MCU damage.
I hope it helps you.
Thank you for the suggestion. I have run a few more tests, here are what I did:
1. I have added the (__asm (CLI); after I enable the LVI to clear the I-bit in CCR register. Then decrease the Vsup to try to trigger the LVI but not work
2. I have tested the LVRF for low voltage reset for VDDX. I decreased the Vsup to aroung 3.5V, then I saw my debugging reset, then I increase the Vsup to 4.5V, then click reset in the debug window to reset the chip, then I am able to see the CPMURFLG.LVRF = 1, which means the VDD/VDDX got low voltage, and a reset has happened. Actually this give me some confidence about the low voltage reset.
3. For the hardware, I checked our schematic with the figure shown below in the datasheet. I don't find any difference.
Here is what I want to confirm with you, if the LVRF works fine, should the LVI mechanism also work since the LVIA for LVI is 4.23V which is higher than the VLVRXA for LVRF?
Correct me if I am wrong. Very appreciated for your support.
Bad to heart, that LVI still doesn’t work.
Unfortunately, I don’t have here now the regulated power supply for testing it. I am planning to pick-up it from office and write an example code for you. Please be patient.
Regarding Low Voltage Reset)
Just be aware, that LVRF flag isn’t affected by system reset (only by clearing or by Power-on Reset). So, we should clear this flag (write log 1) prior to testing low voltage reset.
The low voltage interrupt may be used for various reasons. But most typically the customer uses it as an early warning that voltage falls and we should interrupt Flash/EEPROM operations, stop communication, stop/park motor… depending of the target application area. It also informs us, that we should take the ADC results with reserve - the reference voltage moves with VDDA.
The low voltage interrupt flag should be raised in case of low voltage status change. So, when VDDA falls under 4.23V or when VDDA rises above 4.38V. We must clear this interrupt flag prior to interrupt enable (and inside LVI interrupt routine).
During the LVI testing, low voltage reset must not happen = the VDDA/VDDX must not fall under 3.02V.
Thank you for your explanation, that is really helpful. Also, thank you so much for your support.
Good news here, based on your suggestion, I did a detailed check on the configuration might effect the LVI, now I think I got the LVI working now. I think there is two main reasons cause the LVI not get triggered:
1. The LVI interrupt priority is very low, it is 1, I am thinking could be the reason when some other interrupt, i.e. ADC finish conversion is requesting interrupt, which has higher priority that cause LVI not triggered;
2. The BATS Voltage Low Condition Interrupt (BVLI) is the main reason I didn't catch the LVI, in my software, when the Vsup dropped to 5.5V, the BVLI got triggered then report to the OS to execute a system reset, but the flag of BVLI never got cleared.
Now, my software is able to trigger BVLI when Vsup dropped to 5.5V, then LVI got triggered at Vsup around 4.2V.
It looks good to me now. For the LVRF, I understand your suggestion, I will continue test it. What I want is when Vsup dropped to 3.5V, LVRF got set, then a system reset happens, at the initialization stage of the chip, I read out the LVRF to report to the chip for the reset reason.
Thank you again for all your suggestion and support.
Yes, I am sure about that, I checked the CPMULVCTL_LVIE bit = 1 which means the LVI is enabled. Please let me know if you have any suggestion.