The S12ZVC flash or eeprom erase and progarm will cause CPU core Machine Exception when interruption of power supply.I want to use LVI ISR to stop flash or eeprom erase and progarm before lost power.
But I cannot find the way to stop flash or eeprom erase and progarm.
Loss of power itself doesn't cause machine exception. Machine exception happens later when you power up again and try to read partially programmed locations which are not correctable by ECC.
But I cannot find the way to stop flash or eeprom erase and program.
If power is lost it is already to late to stop flash/EEPROM command. LVI monitors VDDA and triggers when it is below ~4V. Though seems not explicitly stated, I think normal flash/EEPROM operation requires 5V. I would use BATS low voltage interrupt instead of LVI. Would be nice if you could provide that voltage regulator input voltage would drop from BATS low event to LVI event slower than it takes to erase flash/EEPROM sector, which would help providing that started NVM command completes and new one doesn't start.
You should also try handling machine exception, which happens reading partially programmed locations. Machine exception is unfriendly since return address is not easy to calculate. MMCPC points to instruction which could cause exception. If it was read data from bad ECC location, return to the same instruction could cause boot loop. It is also not known which EEPROM location had bad ECC. So I found it necessary to be ready for ME each time I read any piece of data from EEPROM. I handle EEPROM exception like this:
void ReadEepromByte(void *src, char *dst)
*dst = *(char*)(src); // read may lead to jump to ME handler
NOP // NOP is single byte instruction
NOP // amount of NOPs to replicate longest S12Z instruction
// ME handler may set EeepromECCUncorrectable byte variable
// If it's set, fixecc() will erase location with uncorrectable ECC and
// reset EeepromECCUncorrectable to 0.
static void MachineException(void)
LEA S, (-3,S) // reserve space for return address
PSH ALL // save all registers
LSL.B D0, MMCECH, #4 // inspect MMCECH.TGT register
CMP D0, #3 << 4 // MMCRCH.TGT == 3/*EEPROM*/?, is it read from EEPROM exception?
// yes, read from EEPROM exception
ST D0, EeepromECCUncorrectable // signal to fixecc() last read location
// had bad ECC
LD X, MMCPC // read PC of instruction which caused ME
LEA X, (11,X) // skip to one of NOPs in Readxxx() function
// longest instruction is 11 bytes. please fill location
// after EEPROM read access with NOPs
ST X, (26, S) // store return address
RTI // return to read EEPROM
// for everything else loop forever
DEBUGPIN25_PORT ^= DEBUGPIN25_PIN;
Thanks for your suggest.I will revise the circuit design and add machine exception recovery.
But I want to knowning how to stop erase or program commond operate.If the operate cannot be stop,I would revise the erase or program code by add flag check before erase or program.Once find the BVLC bit or BVLIF bit be setted,I will wait the old operation complete and give up new operation.
Can this be achieved?or you have another advise.Tks!
As far as I know flash module doesn't have command to interrupt program or erase command. Even if it had, just think about what you would get with it? I think you would had again partially programmed or partially erased cells .. with unrecoverable ECC errors. The idea with BATS low and long enough VSUP capacitor is that you 1. don't start any new erase/program while VSUP voltage is low (this is what you wrote about give up new operation). 2. long enough VSUP capacitor has enough energy to let MCU complete any erase/program command before reaching low voltage reset threshold. This should eliminate ME's due to incomplete program/erase due to voltage loss. I still recommend you implementing bad ECC ME recovery.
BTW does you circuit have reverse polarity protection diode? It is required to prevent VSUP cap premature discharge by external higher load on VSUP rail.
As Edward already mentioned, the BATS module can trigger a interrupt when VSUP drops below a certain voltage level.
The time between this BATS warning and LVR depends on the power consumption and the VSUP bulk cap.
The NVM timing characteristics can be found in Appending K, S12ZVC RM rev2.