Hi,
Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full-Stop Mode (PSTP = 0 or OSCE=0) and Pseudo-Stop Mode (PSTP = 1 and OSCE=1).
So, to enter Full-Stop Mode, the external clock must be disabled.
Since the Bus clock is stopped in Full-Stop mode, you can monitor bus clock as ECLK on PT7 provided ECLKCTL[NECLK] = 0.
The current is probably increased by ADC if you use it.
Please refer to Mask Set Errata S12ZVC_ON23N.
E8188, ADC: High current in Stop Mode.
The ADC can take a higher current in Stop Mode if the ADC is enabled and conversions have been done.
There is also a workaround. ADC soft-reset must be executed before the MCU enters Stop Mode.
Regards,
Daniel