Hi,
The WR and RD signals are controlled by the internal on-chip bus controller so these pins are not intended to be directly controlled by software. These signals are generated automatically when you read or write the memory area mapped to external space. The chip can also generate one or more chip-select signal(s) for you, each assigned to the specified memory area.
The external bus can be configured by using the CPU bean properties within the group 'external bus' .
You can see more details about the address bus operation in the 56F8367 Reference Manual and also in the manual for the evaulation board for this CPU (there is also a schematics for connecting exteral memory).
Processor Expert projects created using File / New.../ Processor Expert stationery already contains a pre-configured CPU bean using external memory for program and data spac (just select 'sdm external memory' under Configurations).
best regards
Petr Hradsky
Processor Expert Support Team