HCS12 external SRAM (MEBI) with E-CLK at 25 MHz

[jameshdx80]

Hi,

We have been using (MC9S12DP512 at 50 MHz) with an external SRAM memory successfully for more than a decade. Our design replicates the circuit from Example #1 Byte-Wide SRAM Interface (Narrow Mode) ECLK Gated from AN2408/D (Examples of HCS12 External Bus Design).

Since we didn't perform a complete research by that time, we had to use a MCU clock stretch lowering our external frequency from 25 MHz (E-CLK) to 12.5 MHz.

Now, we will redesign our external SRAM memory to achieve maximum performance. Therefore, we will use as reference Example #5 - Word-Wide SRAM Interface (Wide Mode) XCS/ECS Gated. We have been studying this design for a few weeks and I have the following questions:

1. Can this design work (Example #5) with E-CLK at 25 MHz?
We could not find any mention about it in  AN2408/D or AN2287/D. We believe this design won't work at 25 MHz due to the chosen latches and decoders high tpds.#

2. Is it possible to make this design work with E-CLK at 25 MHz?
We believe the answer is yes if the fastest (lowest tpd) decoders and latches available nowadays are chosen. But we are not 100% sure about it, since timing requirements for MC9S12DP512 are very strict as explained in AN2287/D.

3. If even with fastest decoders and latches available (tpd max around 4 to 5 ns) the design does not work, could an FPGA or a CPLD do the job of decoders and latches in faster (in a lower tpd) than standard logic ICs ?

Thanks in advance.
James

MEBI‌ MC9S12DP512@

[jameshdx80]

Hello Mr. Ladislav,

Thank you very much for your help! It save me a lot of time which I would spend in prototyping and testing. Now it is clear that it is most likely that it won't work as I expected.

I think I should better move on and migrate to S12XE.

Sincerely,

James

[lama]

Hi,

At the beginning I suggest you to use newer XDP512 device. SW is easily to be ported, I can provide SW/HW examples of exbus access and setup. DP512 exbus is an alchemy (see link to a document written by Doron Fael). You will avoid a lot of issues and thinking you want to redesign your HW it is the best to do it now. The XDP512 will remove your issues with exbus and if you do not want to use advanced features of the device you can use it as a DP512. Of course I suggest to check SW but I am sure it will be 99% the same.

(Example#5 will not work with this device !!! See following text…)

Now I would like to copy my answers I provided around year 2005 solving similar issues and which provides answers to your questions. There is small amount of info you alreadu know, but I copy it here as a unit:

A1)

The MCU does not contain XCS and contains ECS pin (PK7, pin 108 112ppin LQFP). However, ECS is not allowed to be used for EXBUS even it is on the chip. ECS pin is not assigned to be used for external chip select. This pin is given for emulation modes – please read AN2287 page 2. ECS pin has meaning only in emulation mode when internal ROM is fully disabled (ROMON bit) and entire program is placed inside external ROM.

For design with DP512 you can use (ONLY) examples #1, #2, #3 and  #8 from AN2408.

Example #1 provides you 16bit address/8bit data access to 16kB external memory if this memory is excluded from internal direct access by means of bit ROMHM (register MISC). (Address 4000~7FFF) Example #2 provides you 16bit address/(8/16)bit data  access to 16kB external memory if this memory is excluded from internal direct access by means of bit ROMHM (register MISC). (Address 4000~7FFF) Example #3 provides you 20bit address/(8/16)bit data  access to up to 512k external memory. the approach requires memory paging during accessing memory.

A2)

ECS and XCS signals are not standard bus signal in fundamental notion.

The HCS12 is designed to be used mainly in Single-Chip applications. Its use of the external bus is not user friendly, and there are several timing (potential negative hold times) that need to overcome in order to form a stable external mode design. You would need a lot of specific experience with the HCS12 bus to resolve these issues in advance.

You can absorb knowledge you need from following application notes.

1) AN2287 - HCS12 External Bus Design.pdf..http://www.freescale.com/files/microcontrollers/doc/app_note/AN2287.pdf

2) AN2408 - Examples of HCS12 External Bus Design_ A Companion Note to AN2287-D.pdf

http://www.freescale.com/files/microcontrollers/doc/app_note/AN2408.pdf

3) A Guide for Motorola HCS12 Expanded Mode Bus-Design and for Connecting an HCS12 Expanded Mode Target to a Nohau HCS12 Full-ICE By: Doron Fael, Nohau Corporation October 20, 2003

http://www.nohau.com/appnotes/hcs12-expanded-mode-guide.pdf

(1.2. Very short multiplexed-address hold-time of 2nSEC after ECLK rise)

As an alternative I would recommend the newer S12X family (MC9S12XDP512) for external mode designs. The S12X external bus is much more user friendly and easy to implement for expanded mode use (no ugly timing in Normal Expanded mode either). It has much less problems in referencing very large RAMs (up to MBytes in size) with the help of the S12X new GPAGE register, or even better using the  RPAGE register through the RPAGE window .

The S12X also has many other silicon improvements over the HCS12 family, and especially for rapid performance increase: It executes to 40MHz bus-speed (vs 25MHz on HCS12), has an improved instruction set as compared to the HCS12 family, and a new, second co-processor named XGate that executes at 80MHz bus speed and is very efficient in I/O intensive tasks. I saw benchmarks that give the S12X between 2 to 5 times performance increase compared to HCS12.

DP512 and XDP512 are 100% pin to pin compatible. But there are some points to consider (especially exbus in your case):

- oscillator module is different:

DP512 provides amplitude controlled Colpitts oscillator, full swing Pierce oscillator, external clocks.

XDP512 provides loop controlled Pierce Oscillator, full swing Pierce oscillator, external clocks.

So, to maintain the compatibility the full swing Pierce oscillator or external clocks configuration have to be chosen.

- expanded bus interface is different. DP512 contains multiplexed interface, XDP512 non-multiplexed interface. Notice that only 144 pin package contains expanded bus interface.

A3)

The S12-S12X compatibility is detailed in the following application note (HCS12 and S12X Family Compatibility):

http://www.freescale.com/files/microcontrollers/doc/app_note/AN2615.pdf

S12XD and S12XE are not pin to pin compatible. It’s detailed in the following application note (S12XD and S12XE Family Compatibility), chapter 10:

http://www.freescale.com/files/microcontrollers/doc/app_note/AN3242.pdf

Or if you want to migrate from S12 to S12XE directly then there’s application note “S12 and S12XE Family Compatibility”:

http://www.freescale.com/files/microcontrollers/doc/app_note/AN3469.pdf

Best regards,

Ladislav

[jameshdx80]

Hello, Mr. Ladislav.

I really appreciated your answer, thank you very much! 

Nonetheless, I fell a bit disappointed because we spend almost two weeks carefully selecting the fastest ICs for glue logic to be used in our circuit which is similar to Example #5. After your message, I read all application notes, Doron Fael's guide in addition to MC9S12DP512 datasheets again. If you do not mind, I have some questions about ECS and Example #5.

lama wrote:

A1)

The MCU does not contain XCS and contains ECS pin (PK7, pin 108 112ppin LQFP). However, ECS is not allowed to be used for EXBUS even it is on the chip. ECS pin is not assigned to be used for external chip select. This pin is given for emulation modes – please read AN2287 page 2. ECS pin has meaning only in emulation mode when internal ROM is fully disabled (ROMON bit) and entire program is placed inside external ROM. 

Although, it is clear that ECS is Emulation Chip Select I could not find the information you wrote at AN2287/D page 2. Instead, at Doron Fael's guide (Expanded Mode guide at page 5) I found this:

- ECS becomes active for all external accesses to the range 8000H - BFFFH for all PPAGE values.

- ECS is a good candidate to be used as the LE signal for an address latch of memory at external addresses in the range 8000H - BFFFH, when accessed by low PPAGE values of 00H - 2FH. 

- In order to make ECS and XCS available on the external HCS12 bus, the EMK bit in the MODE register needs to be set to 1 

The timing that is specified for ECS in the MC9S12D family data sheets for 5V operation is:
. ECS becomes high (if not already high) at least 2nSEC after ECLK fall.
. ECS becomes low not later than 16nSEC after ECLK fall (and before ECLK rise).
. ECS is guaranteed to stay high for at least 8nSEC after ECLK fall and before ECLK rise.

1. If Example #5 does not work at MC9S12D why did Freescale specified several ECS timing requirements at MC9S12DP512's datasheet? (even Doron Fael discussed about these timing requirements in his guide)

2. Why did Doron Fael stated that ECS is a good candidate for LE as used in Example #5? (He also shows how to configure it using MODE register)

As for S12X family, I thought it was a great suggestion. We have considered moving to S12XE since it belongs to the Longevity Program. However, I will leave my considerations about to a future message.

Thanks again, Mr. Ladislav.

Best Regards,

James

[lama · Accepted solution]

Hi,

I am sorry, page 9-10...

Emulation Chip-Select Signal (ECS)When the EMK bit in the MODE register is set, PORTK bit 7 is available as an active-low emulation chip-select signal (ECS). ECS is useful for systems that require an external chip-select signal for memory This signal is intended for systems where internal FLASH memory is emulated with external RAM and it cannot be used as a general-purpose chip select.

Moreover, few words from history from design guy....
The ECS signal is generated only when the device is trying to access the internal flash which has precedence over the external memory, so in order to fetch external data with this signal the entire internal flash must be disabled including the area where the internal program is located.

1. If Example #5 does not work at MC9S12D why did Freescale specified several ECS timing requirements at MC9S12DP512's datasheet? (even Doron Fael discussed about these timing requirements in his guide)

- I can remember my starting period in Motorola when I fought with this peripheral and also needed a help of others to get proper info because documentation was confusing. This device is too old so nobody will change anything.

2. Why did Doron Fael stated that ECS is a good candidate for LE as used in Example #5? (He also shows how to configure it using MODE register)

I think he also did not tested it. The theory provided in the MMC block leads to think that it is possible but still..emulation mode is the rule and the issue is processing program_data instructions. It does not split between data and program read.

Finally, examples are also described in a little bit confusing way. The best is to connect the MCY to analyzer or oscilloscope, put the MCU in required mode and test signals.
I am sorry for that.

Best regards,

Ladislav