Hi Daniel,
Thank you very much for quick response. This code was implemented by someone several years ago. It starts to show issue when we change from HD high voltage monitor assert trip point high (VHVHDHA, Typ 28.3v) to HD high voltage monitor assert trip point low (VHVHDLA, Typ 21.0v). Inside our ADC1 completion interrupt service routine, we pet the watchdog. Because the trip point is reduced to 21.0v, somehow the ADC1 completion interrupt is no longer generated when DC link voltage reaches 21.0v which stops watchdog petting and triggers watchdog reset. I guess it's due to GDU DC link voltage monitor on ADC Channel Internal_3 (Table 1-11) stops ADC conversion somehow.
When voltage is over 20v, we don't care about the ADC result precision. We just want ADC1 completion interrupt is kept generated so the watchdog can still be petted inside the interrupt service routine.
I don’t quite understand the GDU phase multiplexer voltage (Internal_2) and GDU DC link voltage monitor (Internal_3) in Table 1-11. Should both GDU phase multiplexer voltage and GDU DC link voltage monitor be used? Not clear how they are used.
In section 18.4.9 GDU DC Link Voltage Monitor
It says the voltage on pin HD divide by 5 is routed to an ADC channel.
But in section 18.3.2.10 GDU Phase Mux Register (GDUPHMUX), VHD is divided by 12.
GDU Phase Mux Register (GDUPHMUX)
00 Pin HD selected , VHD / 12 connected to ADC channel
Kind regards,
Leon