jmk,
Here's piece of code from my BDM programmer. Mass erase routine for S12A/C/D and S12XA/XD devices looks like follows. HWWrBt12() writes byte using WRITE_BYTE (C0) BDM command. HWWrWd12() writes word using WRITE_WORD (C8) BDM command.
I'm mass erasing Flash first, and then EEPROM, shouldn't matter.
HWWrBt12(0x104, 0xFF); // FPROT all protection disabled
HWWrBt12(0x105,0x30); // clear PVIOL and ACCERR in FSTAT register
HWWrBt12(0x103, 0); //fcnfg not for S12X
HWWrBt12(0x102, 0x00); // clear the WRALL bit in FTSTMOD
HWWrBt12(0x105, 0x02); // clear the FAIL bit
HWWrBt12(0x102, 0x10); // fcnfg, write all
HWWrWd12(0x108, 0); // faddr
HWWrWd12(0x10a,0); // fdata
HWWrBt12(0x106, 0x41); // fcmd=mass erase
HWWrBt12(0x105, 0x80); // start
do{
Delay(); // 150us delay
} while( !(HWRdBt12(0x105) & 0x40)) ; // wait for completion.
HWWrBt12(0x102, 0x0); // fcnfg, write all
// mass erase eeprom
HWWrBt12(0x114, 0xFF); // EPROT all protection disabled
HWWrBt12(0x115, 0x30); // clear PVIOL and ACCERR in ESTAT register
HWWrBt12(0x112, 0x00); // clear the WRALL bit in FTSTMOD
HWWrBt12(0x115, 0x02); // clear S12X FAIL bit
HWWrWd12(0x118, 0); //eaddr
HWWrWd12(0x11A, 0); //edata
HWWrBt12(0x116, 0x41);
HWWrBt12(0x115, 0x80);
delay65ms(); // Don't rely on command complete flag, which is not available on S12C, just wait long enough.