EMC performance

[BFS]

I use MC9S12D64 and want to know that how can I improve EMC (especially ESD- there is master clear event at test and we dont want this) performance of may application. I need some advices about this (especially I want to know that what I have to do for not used I/O's of microcontroller). Thanks...

[Alban]

Hi BFS,

For unused I/O, it is advisable to put them as outputs and tie them via a resistor to a rail.
Be careful to also put as outputs the I/Os which exist as Registers but are not available as pins (when using a smaller package, not all I/Os can be bounded out).
Making sure there is no floating input will also decrease your current consumption (less leakage).

Do you have more info on the test and its failure ?
Which pulse voltage/duration ?
On which pin ?

The µc itself has internal protection and is tested to "IEC Something".

Cheers,
Alban.

[BFS]

Ok, let me to explain my application:

Our product is a control panel (buttons, LCD, some inputs - outputs etc.) We were buying a core module (with on-board processor, RAM, Flash, RTC, and many I/O). And we designed our own core module by using MC9S12D64 and 512KB RAM (by using external bus feature) and RTC instead of old core module.

We use the same pin configuration with old core module. Our purpose was to use new core instead of old core without changing anything in control panel.

For certification we must pass some EMC tests. We passed these tests with old core module. We passed many of them with new module. But failed at ESD test. In this test applied our control panel 8kV (air) and 6kV contact (at the metal surface of panel). Under this test condition MC9S12D64 is getting master clear reset.

I think about first improving core module's PCB two layers to four layers. And some other improvements PCB design. What would you advice me additional? (I think that one of the most critical part of the core is external RAM signals. Especially chip enables, address - data buses. What kind of configuration do you advice me? And I am planning to do all of the unused I/Os configuring output. Do you think that I must tied them to VDD or VSS?)

And for defensive software how can I fill unused program memory area with jump to known place (I saw at AN1263). Thanks...

[Devendra]

Hello,

If you have to pass the EMC tests, your Equipment Ground integrity is important. You have to connect this ground to the EARTH connection, while doing the tests. Also there should not be any significant opening to the circuit to the external atmosphere. An IP65  / Dust-tight enclosure design may help.

This is necessary especially for ESD test, because the charge should be instantly grounded.

Thanks & Regards,

Devendra

[usdkurt]

I know that this is a very old thread, but there are a great many good suggestions on hardening against ESD on this page:

Designing Electronic Equipment for ESD Immunity

Kurt