EEPROM Erase on Power down or up

[ericLGC]

We have a legacy product that is using the MC68HC812A4 micro.  We recently have several units where the EEPROM appears to have been wiped out.  This problem is very hard to reproduce and I don't have very many clues as to why this is happening.

Should I be concerned with power up, power down, and/or resets causing the EEPROM to be wiped out?  Anybody know anything about this?  We are using a DS1233 reset chip with our micro.

Thanks in advance,

Eric

[mroczeks]

Did you solve your problem? We are having fairly similar case with S12XE devices. Moreover we are able to reproduce the problem fairly easy - we close and open supply circuit very quickly (manualy) like several times per second and usually after few tries we have this problem produced. We had a look at voltage waveforms all over our boards and no problems were found.

I would greatly apreciate your help.

Best regards, Szymon

[mroczeks]

Solved it. My app was doing writes into D-Flash on the very first moment after power up.
Processor Expert's function makes D-Flash write with sector backup in RAM.
I was "lucky" enough to face conditions when power was down in the middle of this function - exactly after sector erase and before updated content being writen into sector back from RAM.
So apart from improving supply stability during power on I will have to write D-Flash write mechanism with nonvolatile backup (into some dedicated D-Flash sector instead of RAM).
I did not have enough time yet to look closer to on-board's external watchdog chip operation but it is possible that due to supply stability problems during power up it was that watchdog resetting uC in the middle of D-Flash write function. I believe uC alone would handle those supply conditions better - the watchdog just puts more restriction on supply conditions.

[bigmac]

Hello,

When flash is being erased and re-programmed with data held in RAM, the Vdd supply should be able to hold for a sufficient period to complete the process, should power be removed during the process.  This may involve increasing the bulk capacitance at the output of the voltage regulator.

Additionally, it may be useful to provide an "early warning" of the removal of power, to avoid commencing the erase process for such an event.  If using a linear voltage regulator, this might be done by sensing the voltage at the input of the regulator, on the anode side of the reverse polarity diode, to avoid the delay for the discharge of the regulator input capacitance.

Maybe there is also the possibility of writing the data to two different flash sectors on power up, with one of them having been pre-erased during the previous power down.  The write process alone should be much faster than an erase, followed by a write.

Regards,

Mac

[mroczeks]

Thanks for posting Mac, we figured it all out already and it's all true what you're saying