Hi,
When halting the processor (S12XEP100) in the Codewarrior Hiwave debugger, the processor is always reset by the watchdog (COP) and the code starts running again.
How can I configure the debugger so the watchdog is halted in debug mode? This is an easy option to set on MPC55xx devices but I don't know how to do it in S12(X).
Thanks, Ian
You need to set RSBCK bit in COPCTL register. (Keep in mind that COPCTL register has write once bits, so either write all COPCTL bit once or set RSBCK after COP setup is complete).
Thanks for the help.
By inserting the appropriate instruction 'movb #$40,COPCTL' in some example code I get this to work in a sample project.
However I need the debugger to do it for production testing as we cannot insert that instruction in the production code.
Presumably I can put it in one of the debugger 'cmd' files? But which one and what's the syntax?
Thanks, Ian
The problem is you should let application set up COPCTL first, else it probably will reset RSBCK back to 0. I think you need to make reset.cmd to set breakpoint somewhere after COPCTL setup, go until there, write COPCTL with RSBCK set, then probably delete breakpoint. Something like this
BS 0x4000 // address to stop at, where COPCTL is already setup
GO
WB 0x3C 0x40 // write 0x40/*RSBCK*/ to COPCTL
BC 0x4000 // delete breakpoin