COP watchdog reset is hardware reset. It cannot be debugging via BDM because BDM communication/synchronization is lost during reset. I would like recommend simple LEDs for debugging watchdog reset.
In attachment you can find simple example code for COP watchdog.
You cannot handle this event as standard Interrupt. Standard Interrupt ends by RTI assembler command. COP reset interrupt routine must ending by jump to main program (there is no place where program can return).
I would like notice that code in COP_ISR runs before Start12.c code therefore variables and stack are not initialized. So, I would like to recommend use simplest code as possible.
External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 SYSCLK cycles after the low drive is released. See chapter 2.5 Resets at S12XD RM(page 113).
For detecting COP reset it is necessary that voltage level at RESET pin achieve high level during 64 SYSCLK cycles after RESET pin release. After reset, SYSCLK value is equal to OSCCLK. If we take case when we use 16MHz oscillator, 64 SYSCLK cycles presents 4us.
So, if we have 2.2kOhm pull-up resistor at RESET pin, capacitance at RESET pin should be below approximately 1.8nF. Otherwise we detect POR / LVR / Illegal Address Reset / External Reset.
Note: Simply RC cell, RC constant=Tau=R*C represents time when voltage achieve approximately 2/3 value. Safety detection level for high value at pin is also approximately 2/3 value of VCC. So we can use simply calculation. C<64/(R*fOSC). In calculation we omitted capacitance and internal pull-up of RESET pin.