Hi,
Chapter:
1.12.1 CPMU COP and GDU GSUF configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register are loaded from the flash
configuration field byte at global address 0xFF_FE0E during the reset sequence. The GSUF bit in the GDUF register is also loaded from the Flash configuration field byte at global address 0xFF_FE0E during
the reset sequence. See Table 1-15, Table 1-16 and Table 1-17 for coding.
Table 1-15. Initial COP rate configuration
NV[2:0] in CR[2:0] in
FOPT Register CPMUCOP Register
000 111
001 110
010 101
011 100
100 011
101 010
110 001
111 000
Table 1-16. Initial WCOP configuration
NV[3] in WCOP in
FOPT Register CPMUCOP Register
1 0
0 1
Table 1-17. Initial GSUF configuration
NV[7] in GSUF in
FOPT Register GDUF Register
1 0
0 1
Best regards,
Ladislav