Hi,
Do you use your custom made board? Or is it a Freescale one?
The reset line shouldn’t contain any capacitor (or just very small value like 10nF). Otherwise the COP reset can be recognized as a normal external reset and the vector 0xFFFE will be fetched.
The reason is following:
If the watchdog expires the reset line is forced to zero for 128 cycles and released then. The state of reset pin is checked after next 64 cycles. If the pin is in high state, then the source of reset is recognized as a COP. If the pin is still in low state, then it means that the pin is driven low externally – recognized as an external reset.
If the capacitor is connected then the rising edge is too slow and after 64 cycles the state of reset line can be recognized as a low level. This also says that the external reset signal has to be longer than 192 cycles.
The COP reset behavior is the same as POR reset – the stack pointer is not defined, all registers are in default states. So, the initialization has to be done again. The best way is to take care about critical events in the interrupt and then jump to the _startup routine and run the code like after POR reset.
But, looking in your code, there seems to be problem with the branch instruction i.e. bra _Startup.
In most cases, the jump assmbler instruction is used instead :
asm jmp _Startup;
The thing is that BRA instruction has offset of 256 (-128,127), so if the code is executed somewhere at 0xC000, there is no chance to branch to reset vector (0xFFFE).
Operation of BRA:
(PC) + $0002 + Rel ⇒ PC
Rel is a relative offset stored as a two’s complement number in the second byte of the branch instruction.
Regards,
iggi
