COP and analog die watchdog usage

[gumu]

Dear Sir,

I only use COP, analog die watch dog is disabled。

I'd like to know if it's necessary to enable both?

Thanks!

[Q_man]

In normal mode the uC can NOT reset the analog die using the RESET line. This also means a COP (uC) reset will NOT reset the analog die in Normal mode!

Therefore I recommend to use the watch-dog of the analog die to be able to bring the system (uC and analog die) back to a defined state if the watchdog has to kick.

[gumu]

Hi @Q_man ,

Do you have reference code for window watchdog of analog die?

Thanks!

[Q_man]

Hi Mu,

there is no reference code as such.

Attached some driver code...

The state diagram show the usage / options of the watchdog:

E.g. its possible to enable the wd later after reset. You can change the timeout during operation. You can NOT disable the wd once it's enabled, etc...

[gumu]

Hi @Q_man ,

Thank you for your support! During the debugging of the window watchdog, I encountered a strange issue while trying to configure the watchdog timeout. Here are some screenshots of my step-by-step debugging.

1. system startup and WD_CTL register value is 0

2. after executing D2DInit(), WD_CTL register value is 0x0084

3. initial watch dog with timeout value 1024ms, the content of WD_CTL register is changed to 0x0086,it is the expected result.

4. after calling PCRInit(),the content of WD_CTL register is changed to 0x0084. timeout setting is default value (256ms)

I have checked the operations in the D2DInit() and PCRInit() functions, and there is no write operation to the WD_CTL register. I'm not sure why executing these two functions would affect the WD_CTL. If that's the case, how can I modify the watchdog timeout value?

[Q_man · Accepted solution]

Hi Mu,

your experiment makes sense! Here my comments to your steps 1 to 4

1. before the D2DInit() -> you can not access registers on the analog die
2. after the D2DInit() you can access the registers and get the correct reading (default value) 0x84
3. you write was done
4. the watchdog is always running, even if you have stopped the uC during debugging! That's why the value is changing back to the default 0x84 value after the watchdog has reset the analog die

You can not use the debugger to "debug the watchdog". As said its always running independent of the uC stepping mode. Any debugging has to be done in real time with the code be executed!

The 470nF capacitor might be needed to program (download executable to FLASH) the uC. Basically stopping the analog die to Reset the uC (e.g. every 256ms). The 470nF should ONLY be present when programming and should be removed during debugging/execution. For debugging the watchdog should be disabled by software and the 1st breakpoint should be after the disabling of the watchdog.

Rgds
W.

[gumu]

Hi @Q_man ,

Thank you for your response. The issue is now clear.

[gumu]

void D2DInit(TYPE_D2DCLKDIV ClkDiv)  {
	
	D2DCTL1 = D2DCTL1_D2DIE_MASK | 0xF;									// D2DIE=1; TIMOUT[3:0] = 15 (max timeout)  
	D2DCTL0  = D2DCTL0_D2DEN_MASK | D2DCTL0_D2DCW_MASK | ClkDiv;  		// D2D Enable, 8Bit, !Stop in Wait, D2DCLK=BUS
	D2DSTAT0_ERRIF;  													// Clear D2D Errors
}

extern void ApiWdAnalogDieWtdInit(ENUM_WD_CTL timeout)
{
    B_WD_CTL = timeout;
    ApiWdAnalogDieWtdFed();
}

void PCRInit(u16 PreSc) {
	B_PCR_PRESC = PreSc;
}

[gumu]

Hi @Q_man ,

There is a 470nf capacitor between RESET and GND.

Just now, I conducted an experiment and found that when I enable this capacitor, I can observe that the value of the WD_CTL register changes to 0x0084 after executing D2DInit. In the case of disablement, it is 0x0080. This means that if this capacitor is enabled, the watchdog will be enabled with a timeout value of 256ms. In this case, it is not possible to set the timeout value through software. I have always been unclear about the relationship between the external capacitor and the analog watchdog.

[Q_man]

Hi Mu,

please also see above!
The watchdog operation is independent of the 470nF. The 470nF externally "filters" reset pulses generated by the analog die (RESET_A output) to cause resetting the uC (RESET input).
RESET_A  ---- [blocked by 470nF]  ---> RESET