9S12ZVL Pin Assignment using Processor Expert

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9S12ZVL Pin Assignment using Processor Expert

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huang_hw
Contributor II

Background:

MPU: MC9S12ZVLMLF (48 pins)

Development System: Code Warrior 10.6 Special (with Processor Expert)

 

I try to use Processor Expert to assign the IIC pins. After creating the component under "Components Library", there is now a component called IICO:Init_IIC.

 

Under the Properties Tab of Component Inspector, I can do Pin (assignment).

I choose PT0_IOC0_0_SDA0_RXD1_PWM2_LPTXD0 (pin 22 on 48 pin package) and

PT1_IOC0_1_SCL0_TXD1_PWM0_LPRXD0(pin 27 on 48 pin package) respectively for the SDA and SCL pins.

 

When I tried to configure the "pin open drain" of either SDA or SCL pins from "push-pull" to "open drain", the message is "Port does not support selected open drain".

 

My understanding of IIC is that both SDA and SCL pins must be "open drain". If I am unable to configure these pins to "open drain", does it mean I can never use these pins for IIC? (even if the documentation says that IIC is the "Second Function" of these pins)

 

Would be grateful for any help with this. Thanks.

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RadekS
NXP Employee
NXP Employee

Hi hw,

As you currently mentioned, IIC is the "Second Function" of these pins. It means that these pins are GPIO pins until we enable IIC module. In that case IIC module takes precedence over GPIO function and appropriate SDA, SCL pins will be forced to open-drain state. See Table 2-28. Effect of Enabled Features in RM.

Note: There are few more conditions for routing IIC to PT0, PT1 pins. See Table 2-1. Pin Functions and Priorities for more details.

You probably tried configuring PT0, PT1 as GPIO pins with "open drain" feature – it could be set in WOMx registers. However this GPIO feature on S12ZVL is available only for port S and J. See Table 2-27. Bit Indices of Implemented Register Bits per Port in RM.


I hope it helps you.

Have a great day,
RadekS

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RadekS
NXP Employee
NXP Employee

Hi hw,

As you currently mentioned, IIC is the "Second Function" of these pins. It means that these pins are GPIO pins until we enable IIC module. In that case IIC module takes precedence over GPIO function and appropriate SDA, SCL pins will be forced to open-drain state. See Table 2-28. Effect of Enabled Features in RM.

Note: There are few more conditions for routing IIC to PT0, PT1 pins. See Table 2-1. Pin Functions and Priorities for more details.

You probably tried configuring PT0, PT1 as GPIO pins with "open drain" feature – it could be set in WOMx registers. However this GPIO feature on S12ZVL is available only for port S and J. See Table 2-27. Bit Indices of Implemented Register Bits per Port in RM.


I hope it helps you.

Have a great day,
RadekS

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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huang_hw
Contributor II

Thanks Radek for the clarification. Now I can confidentally use these two "second function" pins for IIC.

I assume I can ignore the "Bug" in Code Warrior->Component Inspector IIC0's PIN configurations.

I was earlier unsure because the IIC configuration in my Code Warrior Component Inspector for the IIC module has Pin configuration for the SDA and SCL pins that are set to "SDA/SCL pin open drain" = push-pull and it gives an error message of "Port does not support selected open drain" when I try to set it to open-drain.

(See image below where I tried to set the SDA pin to open-drain)

CW_IIC_config.jpg

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RadekS
NXP Employee
NXP Employee

Hi hw,

Thank you for screenshot.

It really looks like error in PE configuration.

Anyway, this settings is probably related to pin configuration prior we enable IIC module.

When we enable IIC module, module will overtake driving of these pins despite on previous GPIO settings (except routing).

I will report this issue..

Thank you.

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huang_hw
Contributor II

Thanks again Radek.

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