9S12DP512 SPI port 1 and 2 does not work

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9S12DP512 SPI port 1 and 2 does not work

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MTopward
Contributor I
Hello All,

I am in the early stages of using a MAX6675 with a 9S12DP512.  A scope is connected to the SS and
SCK pins.  On SPI port 0 the SS pin goes low and there is a pulse train on SCK but using the same
code with the other two ports there is no activity on the SCK pin.  Any help would be much Appreciated.

CodeSec:     SECTION

IniSPI1                    ;Initialize SPI Port 1
    bset    PORTH,#%10000000      ;Set SS high
    bset    DDRH,#%11100000        ;MOSI, SCK, SS output MISO input
    movb    #$77,SPI2BR                 ;Set baud rate 12.21KHz
    movb    #$10,SPI2CR1               ;Master is 1
    movb    #$08,SPI2CR2
    ldaa    SPI2SR
    ldaa    SPI2DR
    bset    SPI2CR1,#%01000000    ;Enable SPI
    rts

;--------------------------------------------------------------------
; Temperature
;--------------------------------------------------------------------

PPCT
    ldaa    #'T'
    bclr    PORTH,#%10000000
    staa    SPI2DR
   
FLAG
    brclr    SPI2SR,#$80,FLAG
    bset    PORTH,#%10000000
    ldaa    SPI2DR
    jmp    PCX


    END
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6 Replies

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kef
Specialist I
MTopward,
to send data you should clear SPTEF flag. And you clear SPTEF reading from SPISR, then writing to SPIDR. And your code at PPCT just writes SPIDR.
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Stephen
Contributor III
Hi
I am currently using SPI interfaces on a 9S12A256 (only 256kB Flash) but should be same as your processor.

Two thoughts:
1. In my code, I am also setting bit 6 of control register 1 - that's the SPI System Enable Bit

To quote the manual "This bit enables the SPI system and dedicates the SPI port pins to SPI system functions.
1 = SPI port pins are dedicated to SPI functions.
0 = SPI disabled (lower power consumption)."

2. Don't forget the registers for each port are in different memory locations. E.g. on the A256, SPI0 registers are at memory locations 0xd8 to 0xdf, and the SPI2 registers at 0xf8 to 0xff.

I hope this gets you going
Good luck
Steve
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MTopward
Contributor I
Thanks for the reply,

Tried setting bit 6 in the SPI1CR1 but still no pules train from SCK1 also checked the register addresses
against the documentation and they are correct.  I did toggle the SCK1 bit through the port H register
and it works so it's not a bad chip.  Also tried reading the SPI1SR register just before the write to the
register and still no luck.


Message Edited by MTopward on 2008-11-11 06:27 PM
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kef
Specialist I
OK, and did you route SPI1 and SPI2 to port H? If it's the same like in DP256, then by default SPI1 and SPI2 are routed to port P. See MODRR register description.
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Lundin
Senior Contributor IV
In the oldest DP256 devices, they also had different pinout between SPI0/SPI1 and SPI2. For your inconvenience, the pinout on SPI0/SPI1 was MISO, MOSI, SCK, SS while the pinout for SPI2 was MISO, MOSI, SS, SCK.

I'm not sure if this was fixed in newer masks of that derivate?
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MTopward
Contributor I
Kef,

That was the problem.  With bit 6 in the MODRR register set I now get the clock on PH6 where I had
been looking.  Did not think to check PP6.

Thank you for the help.
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