64M MC9S12XD CPU bus clock

[rthym]

I have a product (04a) using MC9S12XDP512 chip, and it has worked well during the past years.

We developed an updated product 07d based on 04a, a new question occured that puzzled me seriously.

The 04a product uses an external osc of 8MHz, and the bus clock is set to 32MHz. Xgate not used.

The 07a product uses the external osc of 8MHz, due to the task allocation, the bus clock is set to 64MHz to fulfill the large task. Xgate not used. PLL ENDABLED,SYNR = 0x0f,REFDV=0x01.

According to the datasheet, the maximum CPU bus clock is 40MHz. But the 64M bus clock does work in 07a, the timer and tasks are tested OK under 64M bus clock.

I am not certain why this happens and can I use the 64MHz as the bus clock in my product.

[lama · Accepted solution]

Hi,

from the NXP position I can only say that the device is not allowed to be used out of parameters defined in the data sheet. The device is not tested for such a condition and nobody can say what will happen in the future. It really could work, but what about local overheating you can not see because it is somewhere inside. You really have ticking time bomb with hidden time of explosion. I suggest you to either decease SYNR to 0x09 or replace oscillator with value of 5MHz. However, PLL filter values also could be recalculated - attached.
Moreover, there is no guarantee provided by NXP if the device is used out of specifications.
Best regards,

Ladislav

[rthym]

Dear Lama,

Thank you for your suggetsion, it does help a lot.