Hello,
I am trying to boot the LX2160ARDB from an SD card and it is unable to start Linux.
I see the below error message before being returned to the u-boot console (error in bold):
=> NOTICE: BL2: v1.5(release):LSDK-20.12
NOTICE: BL2: Built : 17:12:52, Apr 22 2021
NOTICE: UDIMM 18ADF2G72AZ-3G2E1
NOTICE: DDR4 UDIMM with 2-rank 64-bit bus (x8)
NOTICE: 32 GB DDR4, 64-bit, CL=22, ECC on, 256B, CS0+CS1
NOTICE: BL2: Booting BL31
NOTICE: BL31: v1.5(release):LSDK-20.12
NOTICE: BL31: Built : 17:26:29, Apr 22 2021
NOTICE: Welc
U-Boot 2020.04-dirty (Apr 26 2021 - 17:25:34 +0800)
SoC: LX2160ACE Rev1.0 (0x87360010)
Clock Configuration:
CPU0(A72):2200 MHz CPU1(A72):2200 MHz CPU2(A72):2200 MHz
CPU3(A72):2200 MHz CPU4(A72):2200 MHz CPU5(A72):2200 MHz
CPU6(A72):2200 MHz CPU7(A72):2200 MHz CPU8(A72):2200 MHz
CPU9(A72):2200 MHz CPU10(A72):2200 MHz CPU11(A72):2200 MHz
CPU12(A72):2200 MHz CPU13(A72):2200 MHz CPU14(A72):2200 MHz
CPU15(A72):2200 MHz
Bus: 700 MHz DDR: 2900 MT/s
Reset Configuration Word (RCW):
00000000: 58777738 1c580058 00000000 00000000
00000010: 00000000 0c010000 00000000 00000000
00000020: 05a001a0 00002580 00000000 00000096
00000030: 00000000 00000000 00000000 00000000
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 00027000 00000000
00000070: 08b30000 001d0020
Model: NXP Layerscape LX2160ARDB Board
Board: LX2160ACE Rev1.0-RDB, Board version: B, boot from SD
FPGA: v6.0
SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz
SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz
SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz
VID: Core voltage after adjustment is at 801 mV
DRAM: 31.9 GiB
DDR 31.9 GiB (DDR4, 64-bit, CL=22, ECC on)
DDR Controller Interleaving Mode: 256B
DDR Chip-Select Interleaving Mode: CS0+CS1
WDT: Started with servicing (30s timeout)
Using SERDES1 Protocol: 19 (0x13)
Using SERDES2 Protocol: 5 (0x5)
Using SERDES3 Protocol: 2 (0x2)
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... OK
EEPROM: NXID v1
In: serial_pl01x
Out: serial_pl01x
Err: serial_pl01x
Net:
CS4223: Using software initialization...
CS4223: edc/gain/equalization settings: host: CX/4dB/4dB, line: SR/4dB/4dB
FSL_MDIO1:0 is connected to DPMAC5@25g-aui. Reconnecting to DPMAC6@25g-aui
PCIe1: pcie@3400000 disabled
PCIe2: pcie@3500000 disabled
PCIe3: pcie@3600000 Root Complex: no link
PCIe4: pcie@3700000 disabled
PCIe5: pcie@3800000 Root Complex: no link
PCIe6: pcie@3900000 disabled
DPMAC2@xlaui4, DPMAC3@xgmii, DPMAC4@xgmii, DPMAC5@25g-aui, DPMAC6@25g-aui, DPMAC17@rgmii-id, DPMAC18@rgmii-id
MMC read: dev # 0, block # 20480, count 4608 ... 4608 blocks read: OK
MMC read: dev # 0, block # 28672, count 2048 ... 2048 blocks read: OK
crc32+ Unable to update property /resources/icid_pools/icid_pool@0:num, err=FDT_ERR_NOSPACE
fdt_add_subnode: err=<no error>
fdt_setprop: err=FDT_ERR_BADSTRUCTURE
fsl-mc: ERROR fixing mac address for DPMAC4@xgmii
fdt_add_subnode: err=<no error>
fdt_add_subnode: err=<no error>
fdt_add_subnode: err=<no error>
fdt_add_subnode: err=<no error>
Hit any key to stop autoboot: 0
Device: FSL_SDHC
Manufacturer ID: 3
OEM: 5344
Name: SC16G
Bus Speed: 50000000
Mode: SD High Speed (50MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 14.8 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
MMC read: dev # 0, block # 26624, count 2048 ... 2048 blocks read: OK
fsl-mc: Deploying data path layout ..ERROR (MC is not booted)
I refer to "lsdkug"_ "Rev20.12. PDF" manual compilation and " Table 22. Unified 64MiB memory layout of NOR/QSPI/XSPI/NAND/SD media for composite firmware on all Layerscape platforms"
Any help would be appreciated, thanks!
