What is the clock rate between P2010 DDR controller and SDRAM part?

[xiao-dong_wang]

I have a P2010NSE2HHC processor. For the DDR controller, when DDRCLK input is 66.7 Hz and cfg_ddr_pll[0:2] is set to 0b100 (10:1 ratio), is the DDR controller running at 667MHz and the clock between the DDR controller and the SDRAM part running at 333MHz?

Thank you

[xiao-dong_wang]

For the P2010NSE2HHC, would the maximum for the DDR controller clock be 800MHz and so the clock between the DDR controller and the SDRAM part would max out at 400MHz?

Thank you

[Bulat]

Yes, MCK frequency would be 400MHz and data rate - 800MT/s.

Regards,

Bulat

[Bulat]

Yes, that is correct.

Regards,

Bulat