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See Figure “Clock subsystem block diagram” in the LS1021A reference manual (chapter 4). There is Platform PLL which multiplies SYSCLK and provides platform clock. It should be in range 250 – 300 MHz. TPlat is platform clock cycle duration. Platform clock is applied to the SPI controller and to the QUICC Engine.
The TDM hardware maximum frequency is 50 MHz. This device supports TDM in a high-speed mode. To run in this mode, the QUICC Engine platform to TDM interface frequency ratio should be at least 8:1. For the ISDN protocol, the QUICC Engine platform to ISDN interface frequency ratio should be at least 16:1.
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