We are using 2Gb Parallel NOR flash and connected to LS1043A using IFC interface. We are using external transceiver to demultiplex address and Data lines of IFC_AD[0-15]. For 2Gbit addressing we need 27 address bits and 16 data bits.
So, we are connecting as below,
LS1043A NOR
IFC_A[27] - A0
IFC_A[26] - A1
IFC_A[25] - A2
.
.
.
.
IFC_A[2] - A25
IFC_A[1] - A26
In Reference Manual LS1043ARM, In Configuration, Control and Status Register(CCSR) it said that IFC as Big Endian and Byte Swapping Required.
1. Shall we connect as above for accessing 2Gb NOR flash? Please confirm whether we need to connect as address bits in Big Endian or Little Endian?
We are using 16-bit NOR flash, and similar to Address bits, Data bits are also swapped and connected to NOR flash from LS1043A.
2. Please confirm whether we need to connect as data bits in Big Endian or Little Endian?
Correct connection in your case is:
LS1043A NOR
IFC_A[26] - A0
IFC_A[25] - A1
...
IFC_A[1] - A25
IFC_A[0] - A26
IFC_AD[15] - DQ0
...
IFC_AD[0] - DQ15
Refer to the QorIQ LS1043A Reference Manual, 23.9.4.2 NOR flash connections.
1. What should we do with IFC_A[27] pin?
2. Also I'm connecting Two FPGA to IFC interface and we are using 2Mb for both FPGA, so we need 11 address bits. Can you tell me which 11 address bits are recommended to connect to FPGA? IFC_A[26-16] or IFC_A[10-0]?
1) It is not used when 16-bit Flash is connected.
2) The question is not clear.
Is the FPGA byte-addressable?
If "yes", then IFC_A27 is required and will be used as LSb.
IFC is connected to both FPGAs in GPCM mode, one FPGA1 is connected with 11bit address and 8bit data and FPGA2 is connected with 11bit address and 16bit data lines.
Please confirm the Address bit mapping for FPGA-GPCM with 11 address bits.
LS1043A FPGA
IFC_A[27] - A0
IFC_A[26] - A1
IFC_A[25] - A2
.
.
IFC_A[17] - A10
For 8-bit Data connection with FPGA
IFC_AD[15] - DQ0
...
IFC_AD[8] - DQ7
Please confirm Address and Data lines Mapping with FPGA.
Addresses correct.
For 8-bit Data connection with FPGA
IFC_AD[7] - DQ0
...
IFC_AD[0] - DQ7
So for FPGA 11bit address lines we need to use IFC_A[27] to IFC_A[17] and for 8bit Data lines we shall use IFC_AD[7] to IFC_AD[0]. Please confirm if I'm Correct.
I already wrote that.
Thanks for your help