Unable to read Memory Contents of PCIe device

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Unable to read Memory Contents of PCIe device

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iqrajaved
Contributor III

I have configured the PCIe driver as Root Complex according to the requirements mentioned in the reference manual. I am able to read the PCIe controller of the End Point device correctly. The memory region that I have defined in my configuration are read correctly in the BAR0 and BAR1 (lower 32 bits in BAR0 and upper 32 bits in BAR1) registers of the End Point device. But when I try to read the address of memory region I get 0x0 at all the points of memory region. I am also unable to write to any register of the memory region. 

I think the address translation of memory region is not right. Can anyone guide me regarding target address in 64-bit architecture platform? 

The steps i have followed are (for PEX2):

ATU.index register = 0x2;

ATU.Lower base address reg = 0x0;

ATU.Upperbase address reg = 0x4a;

ATU.Limit Reg = 0xffff_ffff;

ATU.Lowe Target Addr = 0x0;

ATU. Upper Target Addr = 0x4a;

ATU.Control1 Reg = 0x0;

ATU. Control2 reg = 0x80000000;

Also, what should be the Memory Base and Limit address for perfect routing? 

Can anyone provide me SDK for LS1046? As i didn't found any.

Regards,

Iqra Javed

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ufedor
NXP TechSupport
NXP TechSupport

Please refer to the Utilizing PCI Express in QorIQ LS Series Processors (FTF-SNT-F1121):

FTF-SNT-F1121.pdf 

The NXP LSDK is available here:

Layerscape SDK|NXP 

232 Views
iqrajaved
Contributor III

I have referred to the Utilizing PCI Express in QorIQ LS Series Processors (FTF-SNT-F1121) document and I have configured PCI according to the steps shown in the document, and I got the same behavior. The problem I am facing is that the Configuration is successful due to which i can read PCIe header of the PCIe device, but when i go to read the memory region at address specified in the lower and upper target address i cannot read the controller registers (I am using NVMe based SSD as a device). I get 0x0 for all the registers. 

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