U-boot produces no serial output on p5020 system

[markpurcell]

I have a strange problem in that an SD card with U-boot will boot fine in a dev system but not in our system. The systems are very similar, only main differences are we are using rev 2 silicon and the dev system has rev 1 silicon, the power supplies, and SERDES configuration.

In our system HRESET_n goes back high after about 750ms, followed by ASLEEP going low 750ms later.

What conditions have to be OK for ASLEEP to eventually go low? Could U-boot be loaded for example, and the core is hung?

Also is there any difference in binary code for rev 2 silicon compared to rev 1 silicon (do apps need to be re-compiled for example)?

Thanks in advance for your help.

Mark.

[lunminliang]

See below technical support comment:

> we are using rev 2 silicon and the dev system has rev 1 silicon, the

> power supplies, and SERDES configuration.

Please provide the power sequencing trace for inspection.

1) Which SerDes configuration is used?

> What conditions have to be OK for ASLEEP to eventually go low?

This behaviour is normal - refer to the P5020 QorIQ Integrated Multicore Communication Processor Family Reference Manual, 4.6.1 Power-On Reset Sequence.

2) What are measured voltages on the LGPL0/LFCLE, LGPL1/LFALE, LGPL2/LOE/LFRE, LGPL3/LFWP, LGPL5 pins when /PORESET is asserted?

3) Do you see activity on the SD interface?

4) Which RCW is used?

5) Are you able to connect a debugger to your board and debug the SD boot?

[marius_grigoras]

Hi Mark,

As far I know it should work for both revisions, we don't set up the processor revision in any configuration SDK/u-boot file before compiling it.

Are you sure that the DIP SW settings are correctly set up? Are you using the same SD card with the same u-boot PBL image?

Regards,

Marius

[markpurcell]

Hi Marius,

As far I know it should work for both revisions, we don't set up the processor revision in any configuration SDK/u-boot file before compiling it.

OK, thanks.

Are you sure that the DIP SW settings are correctly set up? Are you using the same SD card with the same u-boot PBL image?

The SD card is identical, I'm still curious about the ASLEEP signal and how far down the boot process it has got before the processor de-asserts it though.

Are you sure that the DIP SW settings are correctly set up?

Our system uses a CPLD to do the things the SW settings did, but as far as we can see the CPLD is doing the correct things, the system seems to access SD with the same amount of data as the dev board does.

Thanks for your help.

Regards,

Mark.