I have question regarding DDR3L memory interface on T2081.
I'm designing a custom board which will have TwinDie 1.35V Automotive DDR3L SDRAM (MT41K512M16) from micron. In the T2081 DDR Controller interface part I have used only one CS, one CKE, and one ODT.
Please let me know my connection for TwinDie are ok or not as i have read somewhere for twin die DDR interface we require two CS, two CKE and two ODT.
Please find the attached screenshot of my connection. please verify the connection are valid for twin die.
Your schematics looks correct.
Note that there are different 'twin-die' options. Your one consists of two 8-bit dies forming a 16-bit memory device. Of course CS/ODT/CKE are common for both dies. Another option is when two 16-bit dies are used to form a single 16-bit memory device. Yes, in that case each of dies has individual CS/ODT/CKE signals, so finally it is two-rank memory.
thanks for prompt response.
Actually, I am trying to perform DDR Validation using QCVS Tool in codewarrior, but I am getting an error DINIT not cleared by the hardware.
Please let me know how to validate my DDR in my custom board? I am using micron MT41K512M16 and 512MEG x16 in the QCVS configuration tool?
Please help us to provide a path to resolve the issue.
thanks for your response.
Can you help me with any document which help me to verify the DDR Controller setting/RCW setting.
Note: Currently I am using TwinDie 1.35V Automotive DDR3L SDRAM MT41K512M16.
Also, by booting option is set from SPI Boot.
Possible RCW issue mostly relates to RCW[10:15] bits defining DDR clock frequency. This depends on the DDRCLK input frequency.
Take a look at the AN4039 application note, it relates to settings of the DDR controller.