The problem of LS1088A clock

[NaihuaZhang]

As we known,

LS1088A has two clock inputs: SYSCLK and DIFF_SYSCLK/DIFF_SYSCLKB.

SYSCLK: 100-125/133MHz and DIFF_SYSCLK/DIFF_SYSCLKB: 100MHz only.

The DATASHEET shows  SYSCLK "The 125 MHz Max Frequency is limited to parts with 1200 MHz CPU frequency. The 133 MHz Max Frequency can be used  for Parts with 1600 MHz and 1400 MHz CPU Frequency ".

So if I use DIFF_SYSCLK/DIFF_SYSCLKB(100M), can the CPU reach 1600MHz?

[mrudangshelat-13]

Hi @NaihuaZhang,

Note# 6 of table# 13 in the LS1088A datasheet is applicable for the SYSCLK not for DIFF_SYSCLK.

Regards,

Mrudang Shelat

[mrudangshelat-13]

Hi @NaihuaZhang,

Yes, You need to configure the PLLx_RAT as per the requirement.

FYI, Parts with 1200MHz CPU frequency will have max input SYSCLK frequency upto 125MHz. And parts with 1600 MHz and 1400 MHz CPU frequency can use input SYSCLK upto 133MHz.

Regards,

Mrudang Shelat

[NaihuaZhang]

I select the 1600MHz CPU，and use the DIFF_SYSCLK/DIFF_SYSCLK_B （100Mhz）,
I see no problem with that.