TX Buffer Initial Transmission Issue on LS1046ARDB

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TX Buffer Initial Transmission Issue on LS1046ARDB

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Em31
Contributor II

Product Information:

  • Board Model:   
  • Flash Chip: Micro Serial Nor Flash chip

Issue: When performing a flash page program command, an issue occurs with data transmission from the TX buffer. The initial data transmission behavior exhibits anomalies before resuming normal operation.

  • During the first transmission from the TX buffer, the first word of the data transmitted is 0, followed by valid data until the first time buffer is fully transmitted (16 words).
  • the operation is repeated with smaller transmissions:
    • 4 words at a time: The first word sent is 0, and the following three words contain the correct data. This pattern continues for four transmissions before normal operation resumes.
    • 8 words at a time: The first word transmitted is 0, followed by seven words of correct data. This pattern continues for two transmissions before normal operation resumes.
    • Em31_0-1730764188511.png

       

Checking/Debugging:

  • Cleared TX FIFO: Confirmed TX FIFO was cleared before initiating programming.
  • Checked QSPI Flags:
    • QSPI_FR[TBUF]: Indicates no underrun condition.
  • TX Buffer Fill Level:
    • QSPI_TBSR[TRBFL] correctly shows the TX buffer fill level, indicating no overflow.
  • QuadSPI Status Checks:
    • Reviewed QuadSPI_SR and QuadSPI_FR flags; all appear correct with no unexpected indicators.

Questions:

  • What could be causing the initial 0 words in the transmission despite clearing the TX FIFO?
  • Are there any additional configurations or flags to check to ensure proper transmission behavior from the start?
  • Could this issue be related to any known hardware or firmware limitations or bugs?

 @yipingwang @June_Lu 

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yipingwang
NXP TechSupport
NXP TechSupport

We are doing investigating.

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Em31
Contributor II

It appears that clearing the TX FIFO with the CLR_TXF and CLR_RXF bits in the QuadSPI_MCR register only works correctly after performing a software reset on both the AHB and serial flash domains. Post-reset, the TX FIFO behavior aligns with expectations, and the values in QuadSPI_FR and QuadSPI_TBSR registers are as anticipated.
Could you confirm if this workaround is recommended or if it’s an indication of a potential misconfiguration?

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yipingwang
NXP TechSupport
NXP TechSupport

This behavior is not observed on the LS1046A device. You can use the mentioned workaround if that works fine to you. If needed, we will share the QSPI driver file for your reference in case you are missing anything.

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