It appears that clearing the TX FIFO with the CLR_TXF and CLR_RXF bits in the QuadSPI_MCR register only works correctly after performing a software reset on both the AHB and serial flash domains. Post-reset, the TX FIFO behavior aligns with expectations, and the values in QuadSPI_FR and QuadSPI_TBSR registers are as anticipated.
Could you confirm if this workaround is recommended or if it’s an indication of a potential misconfiguration?