TA_BB_VDD power sequencing

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TA_BB_VDD power sequencing

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maxime_guillot
Contributor III

HelIo,

Is TA_BB_VDD can be supply whenver if the other power supplies are present or not?

Can I supply TA_BB_VDD even the SoC is OFF?

Thank you

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ufedor
NXP Employee
NXP Employee

Which exactly processor is in question?

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maxime_guillot
Contributor III

LS1046A

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ufedor
NXP Employee
NXP Employee

The portion of the Security Monitor which is only on while the SoC is powered is referred to as the High Power (HP) section; the battery-backed portion is referred to as the Low Power (LP) section, and the TA_BB_VDD pin is the power supply to the LP section.


TA_BB_VDD should be connected to a power management IC (PMIC) which supplies 0.9 V or 1.0 V (same as VDD) from system power while the system is on, and switches to the supply source to a battery when the system is powered off.

There are special power sequencing and clocking requirements when using the battery-backed Security Monitor features on Trust 2.1 devices. Specifically, before allowing VDD to ramp up to the 0.5 V level, ensure that:
• OVDD has ramped to the recommended operational voltage
• DIFF_SYSCLK/DIFF_SYSCLK_B is running. This clock pair should have a minimum frequency of 800 Hz and a maximum frequency no greater than the maximum supported system clock frequency for the device.

Use of the LP section is optional.

If a Zeroizable Master Key or monotonic counter aren’t required to meet system trust objectives, TA_BB_VDD should be connected to VDD.

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maxime_guillot
Contributor III

In our design we use the LP section.

If the TA_BB_VDD is supplied with the battery when the SoC is OFF and then Soc is turned ON how the requirement of "OVDD has ramped to the recommended operational voltage" is met whereas TA_BB_VDD is already ON when SoC is OFF?

If I switched TA_BB_VDD on VDD when I power the SoC then TA_BB_VDD will switch off until OVDD has ramped and Zeroizable Master Key will be deleted, right?

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ufedor
NXP Employee
NXP Employee

Please consider that the requirement in question is about VDD - not TA_BB_VDD

If LP is used then TA_BB_VDD voltage has to be maintained stable always - ether when the whole SOC power is on or off.

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maxime_guillot
Contributor III

Ok, in the datasheet page 56, TA_BB_VDD is in step 2 si it was a bit confusing.

Thank you

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