T2081 Reset Circuit

[hemanttiwari199]

Hi,

Can anyone tell me how i can design power on reset and hard reset for T2081 processor?

[r8070z]

As example see Figure 2-2. Reset architecture in the QorIQ T2080 Reference Design Board User Guide.

https://www.nxp.com/docs/en/user-guide/T2080RDBPCUG.pdf

Also please see Figure 3. JTAG interface connection in the T2080 Design check list https://www.nxp.com/docs/en/application-note/AN4804.pdf

If you do not need the JTAG/COP interface you can connect PORESET and HRESET signals directly to the T2081. As you can see on Figure 2-2 the PORESET signal can be provided by the MIC811

https://www.microchip.com/wwwproducts/en/MIC811

HRESET signaI can be generated by univibrator (like the NE555) triggered by the T2080 HREST_REQ  output, notice the univibrator ouput has to be open drain.

[hemanttiwari199]

In my design, i am not using CPLD. So, Without having CPLD how i am going to achieve reset circuit and its functionality? 

Regards

Hemant

[r8070z]

Without CPLD the PORESET signal can be provided by the MIC811. 

HRESET signaI can be generated by univibrator (monostable multivibrator) triggered by the falling edge on the T2080 HREST_REQ  output, notice the univibrator ouput has to be open drain. See Monostable Multivibrator Circuits for example on

https://www.electronics-tutorials.ws/sequential/seq_3.html

[hemanttiwari199]

Hi, 

Thanks for the delayed explanation.

Based upon your feedback, i have modified the circuit. Please check and let me know if any changes need to be done.

Regards

Hemant

[r8070z]

Actually according to the manual the RESET_REQ_B requests that PORESET_B be asserted. So my simple suggestion for univibrator applied to the HRESET_B is not reliable, sorry. However if the poreset chip and univibrator have open drain outputs then we can connect both to the PORESET_B input.
Also PORESET_B assertion should also reset SDRAM Memory. Hence the level translator has to be driven by signal applied to the PORESET_B. Using your components I reconnect them in the next way

Of course you can find better way to OR the push buton and Reset_Req_B signals.

[hemanttiwari199]

thankyou for your valuable suggestion.

Just have a small doubt, if i am using the same suggestion mentioned by you, do i have to change the IC's having open drain output? Also, hard reset should be done automatic or manually i.e via external switch or hardware? Also, what about Hreset Pin, where to connect it or should i leave that pin unconnected?

Can i use MAX6315 for both power on reset as well as hard reset?

Regards

Hemant

[r8070z]

If you do not need implement JTAG interface (see the design checklist) then you can connect HRESET_B pin to pull-up resistor only. For reset assertion to the chip, use only PORESET_B. PORESET_B also initiates the HRESET sequence (see in the manual). PORESET_B is an input and does not require for the open-drain (by the way the MIC826 outputs are not open-drain). You can use MAX8315 (or MIC826) if you add the AND gate which assigns its /MR input when the push-button is pressed or RESET_REQ output is low.

[hemanttiwari199 · Accepted solution]

Hi, thanks for the prompt response.

Here i am attaching the modified design, please verify it and let me know if any corrections are needed or not?

[r8070z]

Yes it is suitable reset schematic for the T2081.

[hemanttiwari199]

Hi,

there is little modification in my circuit. We have added COP connector for debugging. I have connected the cop header with jtag pins as recommend in the T2080 reference design. 

But I am not able to understand the logic of HRESET, COP_TRST_N and JTAG reset pin? how to make effective cop debugging connection. we are not using any CPLD\FPGA in our design. 

In one of the document it is return that HRESET should be tied to jtag reset pin of t2081 using 0 ohm resistor?

Attaching the Image for your reference.

Regards

Hemant