Hello,
Currently i am working on the device is based t2080 processor.
In the design i am only using one Ethernet phy i.e. RTL8211E-VB.
As i am not using 10G EDC PHY CS4315, can i connect the SD1_REFCLK2 and SD1_REFCLK2 to U47 ICS843002-01? If yes, then why it is not connected in the reference design?
To understand better, i am enclosing the image for the same.
Waiting for your reply,
Regards
Hemant
Please refer to the following picture:
to realize that SD1_REFCLK1_P/N is 156.25MHz and SD1_REFCLK2_P/N is 100MHz
In the image that you have shared above show SD2_REFCLK1_P/N AND SD2_REFCLK2_P/N are coming from IDT9FGV0641 but in the reference design SD2_REFCLK2_P/N is coming out from IDT9FGV0641 while SD1_REFCLK2_P/N is coming from ICS859S0212I?
If i connect both SD2_REFCLK1_P/N AND SD2_REFCLK2_P/N to IDT9FGV0641, is it going to work?
As i can see in the schematic that to diff. pair are free in IDT9FGV0641?
Waiting for your reply!!
It is not clear what are you intended to do.
Please provide the proposed block diagram and corresponding SerDes1 & 2 protocols which you plan to use.
I am not using any kind of the PCIe connector in my design,
and according to picture shared by you both SD2_REFCLK1_P/N and SD2_REFCLK2_P/N both having frequency of 100MHz.
my question is whether i can connect both the SD2_REFCLK1_P/N and SD2_REFCLK2_P to IDT9FGV0641 while eliminating the need of ICS859S0212I IC ?
Attaching the image for your reference?
Regards
Hemant
Please draw and provide the proposed clocking block diagram and corresponding SerDes1 & 2 protocols which you plan to use.
Please ignore the above shared image as it was wrong.
Attaching the final proposed clocking diagram.
Which SerDes1 & 2 protocols you plan to use?
Serdes 2
SerDes Protocols:
etc....
my question is related to clocking. attaching the same for your reference.
Please check and tell me whether the connection that i have made are correct or not as per t2080 reference design?
T2080RDB supports only SRDS_PRTCL_S1=0x66 and SRDS_PRTCL_S2=0x15.
Are the same used in your design?
Showing the proposed clocking diagram. Please check and let me know what you think?
Please ignore the above shared image as it was wrong.
Attaching the final proposed clocking diagram.