T1042D4RDB ASPM Support

[tyler_bush]

Hello,

I have a question regarding the Active State Power Management support on the T1042D4RDB. In the QorIQ T1040RM, page 1526 (link capabilities register), it shows for ASPM support only two options: 

01      L0s entry supported

11      L0s and L1 entry supported

Does this mean that disabling ASPM is not possible? I've tried to write to this ASPM 2-bit field unsuccessfully via PEX_CONFIG_ADDR/PEX_CONFIG_DATA. The PCIe  spec states "Root Complexes are required to participate in Link power management DLLP protocols initiated by a Downstream device"......is this why L0s entry must be supported, at a minimum? If L0s entry is supported, does that mean that the RC (T1042) is able to detect idle and go into a low power state (L0s), or only that it supports requests from an EP to do the same?

The analyzer I'm using shows the bus going from L0 to recovery and back, and I'm looking for the cause (suspecting an ASPM situation). This appears to only happen when I change the bus speed (via the EP) to PCIe Gen 2 (5.0GT/s). 

Thank you

[andrei_skok]

The PCI Express ASPM can be disabled in either one of the following options:

• The PCI Express ASPM policy is normally controlled globally by the operating system. If it's feasible, turn off the ASPM support globally in the OS for the whole PCI Express fabric that the device belongs to.

• If ASPM cannot be turned off globally, the ASPM support of the affected device's PCI Express link can be disabled by setting the PCI Express link Control register [ASPM_CTL] = 00b for both the T1042 PCI Express controller and its link partner.

See T1040RM, 28.10.11 PCI Express Link Control Register (Link_Control_Register).