T1042: RGMII (EC2: FMAN MAC5)

[murashimateruhi]

#T1042RGMII: We are using the T1042 processor. And we are using RGMII interface (EC2: FMAN MAC5) for an Ethernet PHY IC. When the T1042 boots up, the EC2 RGMII interface is working from the beginning. And its interace starts communicating with the Ethernet PHY IC through this RGMII interface automatically, after the Ethernet PHY IC starts.

But we would like to start this RGMII interface from the disable condition just after the T1042 boots up. We would like to set this RGMII interface like the following.

1) Even when the Ethernet PHY IC starts, the communication with the T1042 and the Ethernet PHY IC through the RGMII interface is disable.

2) This communication starts after the specific register (software) setting.

Could you tell us the way of this register setting, if there is this register setting?

[faizmajeed]

I think if you have control over any of two pins through registers(GPIO or any CPLD)

1) RESET

2) POWER

then you can do this. At the start up when you want your communication to be disable, you can assert the reset signal and when you think think that its time to start communication you can just disable the reset signal and phy will start.

Same is the case if you have control over power pin.You can power on the phy when it is needed.

Have a nice Day

Faiz

------------------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!    
------------------------------------------------------------------------------------------------------------------------------