T1042 Overshoot Period!

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T1042 Overshoot Period!

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qammarabbas
Contributor IV

Hi,

I am working on T1042's IFC Controller that is being driven by a flash. However, when i simulated my design i found that there is overshoot and undershoot at the data bus on the processor's (T1042) side. The undershoot and overshoot limit as defined by datasheet is 300mV. In my simulations, it is approaching 450mV. I want to know that for how much time period is this overshoot/undershoot acceptable? I searched the datasheet but could not find the required information.  

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alexander_yakov
NXP TechSupport
NXP TechSupport

Overshoot is allowed to be not more than 20% of OVDD for 10% of clock period. See figure below to understand, from which points these "10%" must be measured.

Undershoot is allowed to be "GND - 0.7V" for the same 10% of clock period.

For IFC bus clock period may be very slow, so SYSCLK is used as reference clock period. For frequencies faster than SYSCLK, for example if your SYSCLK is 66 Mhz, but IFC_CLK is 100Mhz, than it will be safe to use actual IFC_CLK frequency value instead of SYSCLK.

pastedImage_1.png


Have a great day,
Alexander
TIC

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alexander_yakov
NXP TechSupport
NXP TechSupport

IFC controller is powered from OVDD = 1.8V, maximum allowed overshoot is 20% of OVDD, which leads to 1.8*0.2 = 360 mV. See Figure 8 in device datasheet.

Overshoot for more than 20% is not allowed, so the value you specified 450mV - is not acceptable.


Have a great day,
Alexander
TIC

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qammarabbas
Contributor IV

Hi Alexander,

Thank you for your reply. Could you please answer the second part as well? The undershoot/overshoot of 360mV should be less than for some amount of time. What is that amount of time?

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alexander_yakov
NXP TechSupport
NXP TechSupport

Overshoot is allowed to be not more than 20% of OVDD for 10% of clock period. See figure below to understand, from which points these "10%" must be measured.

Undershoot is allowed to be "GND - 0.7V" for the same 10% of clock period.

For IFC bus clock period may be very slow, so SYSCLK is used as reference clock period. For frequencies faster than SYSCLK, for example if your SYSCLK is 66 Mhz, but IFC_CLK is 100Mhz, than it will be safe to use actual IFC_CLK frequency value instead of SYSCLK.

pastedImage_1.png


Have a great day,
Alexander
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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