T1042 DDR Prime DQ

[pregache]

Hello, we use DDR3L device from Micron for our memory plane of a T1042 design. The memory uses DQ0 and DQ8 (x16 device) as the prime DQ for the write levelling feature.

Does the T1042 DDR memory controller expects the prime DQ to be connected to MDQ0/MDQ8/... for the write levelling process to work ? OR does it monitor all DQs (within a byte)

The DDR3 controller has DDR_DDR_DQ_MAP registers to re-route DQ (so is my understanding). Does this process take place "in front" of the write levelling engine (I guess so).

Thanks for the clarification

Pascal

[ufedor]

1) The T1042 DDR memory controller monitors all DQs within a byte.

2) The DQ mapping is applied before performing write levelling.

[pregache]

Hello Ufedor, first of all, thank you for the answer.

I have now the same question with the MECC bus: is the T1042 DDR memory controller monitoring all MECC data signals or just one ?

As a matter fo fact, we had our memory running OK so far without ECC. Then as we enable it, the memory fails. The error is always related to the ECC. Dumping (a part of) the memory with the debugger shows that it is correctly initialized by the memory controller with the pattern defined by DDR_DATA_INIT register. And the routing is roughly the same quality as for other devices. Therefore I am left with the leveling process.

Is there any ERRATA related to the T1042 DDR memory controller pending ?

[ufedor]

The ECC lane is calibrated the same way as any other data lane.

You wrote:

>Therefore I am left with the leveling process.

Inability to successfully complete a lane calibration will lead to ACE error - in this case the DDR controller operation will be blocked.

> Is there any ERRATA related to the T1042 DDR memory controller pending ?

Errata is a confidential document which could be provided only under NDA through the Technical Case.

New Case creation:

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2)    Select "Support" -> "All Support Options"
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