[T1040QDS] [eSPI] ESPI_SPCOM[DO] clarifications

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[T1040QDS] [eSPI] ESPI_SPCOM[DO] clarifications

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rommelcustodio
Contributor I

Dear All, Freescale Engineers,

Now studying the eSPI block but I can't find any AppNote about eSPI and ESPI_SPCOM[DO].

The connected serial NOR flashes seems to support Dual mode.

So I'm modifying FSL u-boot 2013.10 (the usual suspect) and working with CS#0 (Micron part).

I'll be referring to T1040RM_RevC.pdf in the text below.

Kindly correct any mis-understandings:

1) ESPI_SPCOM[DO] affects DQ[1:0] for both INPUT and OUTPUT OR only during OUTPUT only?

In my mind, the statement in 20.5 seem to imply that ESPI_SPCOM[DO] affects DQ[1:0] only during OUTPUT.

The answer to question 1) affects my other understanding.

If ESPI_SPCOM[DO] is only for OUTPUT that means I do not need to program the Serial NOR device to Dual mode.

For example sending the DUAL OUTPUT FAST READ , in Dual mode, the Micron expects Address INPUT to use also DQ[1:0].

Though in Extended mode, Address INPUT is thru DQ0 but Data OUTPUT can use DQ[1:0].

2.a) ESPI_SPCOM[DO] can be enabled on a transaction basis.

For example, use READ ID (with ESPI_SPCOM[DO] = 0), then start a FAST READ (with ESPI_SPCOM[DO] = 1).

OR

2.b) ESPI_SPCOM[DO] is persistent until the next power cycle.

From statement in 20.3.4, my understanding is ESPI_SPCOM[DO] must be set for very first command send to Serial NOR device.

Device detection should not use READ ID. This means that Serial NOR device (Micron) must be also in Dual mode prior.

Here lies a chicken-and-egg problem since I want to program the Dual mode in the Enhanced Volatile Configuration Register only

(i.e. the Micron will always reset to Extended mode after a power reset).

3) It seems drivers/spi/fsl_espi.c:spi_xfer() does not check ESPI_SPIE[DON].

Though it seems it doesn't really matter since we can only perform one transaction at a time in u-boot.

4) What other settings affect ESPI_SPCOM[DO]?

Do you have equations for the correct calculation of ESPI_SPMODE[HO_ADJ]?

Your expertise will be highly appreciated.

All the best,

Rommel

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r8070z
NXP Employee
NXP Employee

 

I will refer to T1040RM_RevC.pdf too. Chapter 20 Enhanced Serial Peripheral Interface provides ESPI description in details

 

1) T1040RM says that “ESPI Interface contains SPI_MOSI, SPI_MISO, SPI_CLK, and 4 chip selects”. For ESPI_SPCOM[DO] it says:

"This mode is useful only for character lengths of 4,6,8. 

DO and RapidS should not be set simultaneously.

DO=0 Normal eSPI operation

DO=1 Winbond dual output read-when eSPI master reads data 2 data bits are available (on MISO and MOSI)"

 

Here “normal eSPI operation” means eSPI shifts Tx data out on the "eSPI master-out slave-in" (MOSI) and Rx data in on the eSPI "master-in slave-out" (SPI_MISO).

“eSPI master reads” means the T1040 eSPI reads i.e. its MISO and MOSI are inputs when DO=1. The T1040 eSPI can only be used as an SPI master.

 

 

2a,b) T1040RM shows that all available bits in the SPCOM touched by hardware only on reset. I.e. after reset what you write into these bits what you read. DO=1 has no meaning for eSPI master write.

 

 

3) I do not check the u-boot source but agree with your comment “it doesn't really matter since we can only perform one transaction at a time”


 

4) Please see app. note “QorIQ eSPI Controller Register Setting Considerations and Programming Examples”

http://cache.freescale.com/files/32bit/doc/app_note/AN4375.pdf

 

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