T1040: SFPs over SGMII -serdes inteface

[manjularajesh]

On T1040 base board we are using serdes protocol -0x69 ;we have sgmii interfaces on:

X1 on Lane1-FMmac3

X1 on Lane6-FMmac4

the above sgmii links are connected  directly to SFPs without any PHYs as in RDB.

Do we have to program SerDes_SGMIICCR1, SerDes_SGMIIDCR1 registers to set the dummy phy device addresses?

I added the following lines in u-boot in int misc_init_r(void) function to initialise phy addresses as 0xc and 0xd to lane1-sgmii and lane6-sgmii respectively:

out_be32((unsigned *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR+0x624),

                 0x600008bf);

out_be32((unsigned *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR+0x634),

                 0x610008bf);

u-boot prompt is not coming, after adding above lines.It hangs after executing above lines

please let me know what is the issue.

Thanks in advance,

Manjula

[bpe]

Management addresses set in SGMIInCR1 are _not_ dummy PHY addresses.

They are base addresses of the on-chip PCS slave management ports,  must be

initialized and must be unique regardless of the presence of an external

PHY. It is also required that the on-chip PCS is initialized correctly

in accordance to the auto-negotiation protocol supported by the far end.

Details can be found in T1040RM, Section 31.6.

As of the lockup, it requires debugging. To get in idea why it does not

respond, you have to at least establish where it spins.

Have a great day,
Platon

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[manjularajesh]

Hi,

I have following queries:

I have observed during serdes initialization always port_addr=0

is used in function dtsec_configure_serdes(struct fm_eth *priv) in u-boot.why it should

be 0.

We have 2 sgmii interfaces on mac3 and mac4 and the serdes_sgmiiccr1 &

serdes_sgmiidcr1 MDEV_PORT is pointing to 0, should it be 3 and

4 default values?

fe0ea624: 000008bf 00000000 00000000 80000000 ................

fe0ea634: 000008bf 00000000 00000000 80000000 ................

In u-boot config file should I change the phy addresses of

sgmiis to 3 & 4

#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 /mac3 lane b/port2/

#define CONFIG_SYS_SGMII2_PHY_ADDR 0x04 /mac4 lane g/port7/

In mii info command is given, we donot have phy_interface 0 when 'mii info' is

given in our board. as in oldder boards there used to be phy_inteface 0x1f for TBI.

what is the difference between PCS and TBI.

regards,

manjula

On Wed, 22 Jun 2016 03:37:52 -0700, bpe wrote

bpe replied to

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