T1024RDB SerDes LANE 2 Issue

[abineshselvaraj]

Hi,

We have a custom board which is developed with-reference to T1024RDB. In custom board, the SERDES Lane-1 (SD_TX1_P) is connected with PCIe switch and the  Lane-2 (SD_TX2_P) is connected with Ethernet Switch. Both the Lanes are configured as PCIe through the RCW SERDES protocol configuration(SRDS_PRTCL_S1 = 0x95).

The PCIe switch (in PCIE3) is detected and the vendor-id (0x12d8) is displayed in U-boot boot log. But, the Ethernet switch vendor-id (in PCIE2) is not displayed and the PCIE2 link is down as shown in the log below,

The Ethernet switch is configured in PCIe endpoint mode and it uses PCIe internal clock. Kindly provide your suggestions.

U-boot Boot Log:

SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=100.00MHZ
SPI:   ready
DRAM:  2 GiB (DDR3, 64-bit, CL=11, ECC off)
Flash: 0 Bytes
L2:    256 KiB enabled
Corenet Platform Cache: 256 KiB enabled
Using SERDES1 Protocol: 149 (0x95)
SEC0: RNG instantiated
NAND:  0 MiB
MMC:   FSL_SDHC: 0
EEPROM: Invalid ID (aa 55 aa 55)
PCIe1: Root Complex, no link, regs @ 0xfe240000
PCIe1: Bus 00 - 00
PCIe2: Root Complex, no link, regs @ 0xfe250000
PCIe2: Bus 01 - 01
PCIe3: Root Complex, x1 gen2, regs @ 0xfe260000
  03:00.0     - 12d8:2608 - Bridge device
   04:01.0    - 12d8:2608 - Bridge device
   04:02.0    - 12d8:2608 - Bridge device
   04:03.0    - 12d8:2608 - Bridge device
   04:04.0    - 12d8:2608 - Bridge device
   04:05.0    - 12d8:2608 - Bridge device
PCIe3: Bus 02 - 09
In:    serial
Out:   serial
Err:   serial
Net:
MMC read: dev # 0, block # 2080, count 128 ...
Fman1: Uploading microcode version 108.4.5
Could not get PHY for FM_TGEC_MDIO: addr 1
Failed to connect
FM1@DTSEC4 [PRIME], FM1@TGEC1
Checking failsafe boot..
1 blocks read: OK
Active Partition is: Primary Partion
Safe to go with Primary Partiton
1 blocks read: OK
Ready to boot with bootcmd:mmcinfo;mmc read 1000000 3000 2a30;mmc read 5000000 8800 f600;mmc read 2000000 8000 3f;bootm 1000000 5000000 2000000
1 blocks written: OK
Hit any key to stop autoboot:  0

Thanks,
S.Abinesh.

[ufedor]

> The Ethernet switch is configured in PCIe endpoint mode

> and it uses PCIe internal clock.

What exactly means "it uses PCIe internal clock"?

Note that if different reference clocks are used on both sides of a link the both must be non-spread-spectrum.

[abineshselvaraj · Accepted solution]

Hi ufedor,

Thanks for the reply. 

The ethernet switch is not using reference clock from T1024 SERDES1. The bootstrap or hardware configuration of ethernet switch is configured in such a way that, the PCIe controller in ethernet switch will use the internal clock (which is generated inside the switch).

Thanks,

S.Abinesh.