## T1024RDB Default I2C Bus 2 SCL frequency

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## T1024RDB Default I2C Bus 2 SCL frequency

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Contributor III

Hi,

We are using T1024RDB for our project. We need to change the I2C Bus 2 SCL frequency to 100Khz. It is found that, the default frequency divider value is 0x1031. What is the SCL frequency for this divider value and how to change this to 100 Khz.

Thanks,

S.Abinesh.

1 Solution
509 Views
NXP TechSupport

Have a great day,

The SCL Frequency = Source clock frequency/ Frequency divider.

For the T1042 the source clock frequency is the 1/2 Platform Clock frequency. It is generated by the T1024 Platform PLL. The RCW[SYS_PLL_RAT] and input System clock define it.

The frequency divider is defined by I2CFDR and I2CDFSRR register. There is not simple expression but there are FDR Divider Tables. The calculation details and tables you can find in the application note AN2919 “Determining the I2C Frequency Divider Ratio for SCL”, Rev. 5. You can download it from the nxp site.

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510 Views
NXP TechSupport

Have a great day,

The SCL Frequency = Source clock frequency/ Frequency divider.

For the T1042 the source clock frequency is the 1/2 Platform Clock frequency. It is generated by the T1024 Platform PLL. The RCW[SYS_PLL_RAT] and input System clock define it.

The frequency divider is defined by I2CFDR and I2CDFSRR register. There is not simple expression but there are FDR Divider Tables. The calculation details and tables you can find in the application note AN2919 “Determining the I2C Frequency Divider Ratio for SCL”, Rev. 5. You can download it from the nxp site.

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