Setting CPCSRCR0[SRMSZ] bit in T1040RDB

[hv]

If I set CPCSRCR0[SRAMSZ] to be 00010 (128 Kbytes), does that mean 128 Kbytes can be used as SRAM and the rest of L3 can be used as cache?  Thanks!

[alexander_yakov]

Yes, the remaining part, not used to SRAM, will be used for cache (including stashing, if enabled).

Note - setting only CPCSRCR0[SRAMSZ] is not enough to enable SRAM, please do not forget CPCSRCR0[SRAMEN].

Have a great day,
Alexander

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[hv]

Yes, I remembered the CPCSRCR0[SRAMEN] bit.

Thanks!